公开(公告)号：US20050077571A1

公开(公告)日：2005-04-14

申请号：US10950610

申请日：2004-09-27

申请人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

发明人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L31/113

CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L27/0821

摘要： A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

摘要翻译： 根据本发明的半导体集成电路器件包括在用作小信号部分的岛区中的衬底和第一外延层之间的N型嵌入扩散区域。 因此，衬底和第一外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

公开(公告)号：US06815799B2

公开(公告)日：2004-11-09

申请号：US10437524

申请日：2003-05-14

申请人： Shigeaki Okawa ,  Koichiro Ogino

发明人： Shigeaki Okawa ,  Koichiro Ogino

IPC分类号： H01L2900

CPC分类号： H01L27/0259

摘要： A semiconductor integrated circuit device with built-in spark killer diodes suitable for output transistor protection has a problem such that a leakage current to the substrate is great and a desirable forward current cannot be obtained. In a semiconductor integrated circuit device of the present invention, P+-type first and second diffusion regions 34 and 32 are formed on the surface of a second epitaxial layer 23 in a partly overlapping manner. And, by a connection to an anode electrode 39 at a part immediately over the P+-type second diffusion region 32, a parasitic resistance R1 is made greater than a parasitic resistance R2. Thus, an operation of a parasitic transistor TR2 that causes a leakage current to a substrate 21 is suppressed, whereby leakage current can be greatly reduced.

摘要翻译： 具有适用于输出晶体管保护的内置火花放电二极管的半导体集成电路器件具有这样的问题，使得到衬底的漏电流大，并且不能获得期望的正向电流。 在本发明的半导体集成电路器件中，P +型第一和第二扩散区34和32以部分重叠的方式形成在第二外延层23的表面上。 并且，通过与在P +型第二扩散区域32正上方的部分处的阳极电极39的连接，使寄生电阻R1大于寄生电阻R2。 因此，抑制了导致对基板21的漏电流的寄生晶体管TR2的动作，能够大幅降低泄漏电流。

公开(公告)号：US20080164556A1

公开(公告)日：2008-07-10

申请号：US11862585

申请日：2007-09-27

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC分类号： H01L29/866

CPC分类号： H01L27/0788 ,  H01L27/0255 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/47 ,  H01L29/866 ,  H01L29/872

摘要： There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third anode diffusion layer formed in the epitaxial layer so as to surround the first and second anode diffusion layers and to extend toward the cathode diffusion layers, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.

摘要翻译： 在肖特基势垒二极管中存在反向漏电流变得过大的问题。 本发明的半导体器件包括形成在N型外延层中的P型第一和第二阳极扩散层，在外延层中形成的N型阴极扩散层，形成在外延层中的P型第三阳极扩散层 以便围绕第一和第二阳极扩散层并朝向阴极扩散层延伸，以及形成在第一和第二阳极扩散层上的肖特基势垒金属层。

公开(公告)号：US07381998B2

公开(公告)日：2008-06-03

申请号：US10949569

申请日：2004-09-24

申请人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

发明人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC分类号： H01L29/861

CPC分类号： H01L27/0821 ,  H01L27/0647

摘要： A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.

摘要翻译： 根据本发明的半导体集成电路器件包括在第二岛区中的二极管。 二极管的阳极区域和具有水平PNP晶体管的第一岛区域中的分割区域彼此电连接; 二极管的阴极区域和功率NPN晶体管的集电极区域彼此电连接。 因此，具有水平PNP晶体管的第一岛状区域中的分割区域的电位低于其他岛状区域中的分割区域，从而可以防止自由载流子（电子）向水平PNP晶体管的流入。

公开(公告)号：US20070057321A1

公开(公告)日：2007-03-15

申请号：US11516733

申请日：2006-09-07

申请人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

发明人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

IPC分类号： H01L29/76 ,  H01L21/76

CPC分类号： H01L29/0696 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/7816

摘要： In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

摘要翻译： 在本发明的半导体器件中，MOS晶体管被设置为椭圆形。 分别使用椭圆形状的线性区域作为有效区域，椭圆形状的圆形区域分别用作非活性区域。 在每个非活性区域中，形成P型扩散层以与圆形重合。 另一个P型扩散层形成在一个非活性区域的一部分中。 这些P型扩散层形成为浮动扩散层，电容耦合到绝缘层上的金属层，并且呈现分别施加预定电位的状态。 这种结构使得有可能保持有源区的电流性能，同时提高无源区的耐压特性。

公开(公告)号：US20060220099A1

公开(公告)日：2006-10-05

申请号：US11391166

申请日：2006-03-27

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L29/788

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of the present invention, an epitaxial layer is deposited on a substrate, and an LDMOSFET is formed in one region divided by an isolation region. In a region where a wiring layer connected to a drain electrode traverses a top surface of the isolation region, a conductive plate having a ground electric potential and another conductive plate in a floating state are formed under the wiring layer. With this structure, electric field is reduced in the vicinity of the isolation region under the wiring layer, whereby a withstand voltage of the LDMOSFET is increased.

摘要翻译： 在现有的半导体装置中，存在如下问题：在施加高电位的布线层横越隔离区域的上表面的区域中，耐电压劣化。 在本发明的半导体器件中，在衬底上沉积外延层，并且在由隔离区域划分的一个区域中形成LDMOSFET。 在与漏电极连接的布线层穿过隔离区域的上表面的区域中，在布线层的下方形成具有接地电位的导电板和浮置状态的另一导电板。 利用这种结构，在布线层下面的隔离区附近减小了电场，从而提高了LDMOSFET的耐受电压。

公开(公告)号：US20050082632A1

公开(公告)日：2005-04-21

申请号：US10950611

申请日：2004-09-27

申请人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitaka

发明人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitaka

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732 ,  H01L29/423

CPC分类号： H01L21/8224 ,  H01L27/0821 ,  H01L29/7322

摘要： A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

摘要翻译： 根据本发明的半导体集成电路器件包括用作小信号部分的第一和第二岛区中的衬底和外延层之间的N型嵌入扩散区域。 N型嵌入扩散区域连接到具有电源电位的N型扩散区域。 因此，衬底和外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入式扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。