公开(公告)号：US20100264392A1

公开(公告)日：2010-10-21

申请号：US12742841

申请日：2008-11-14

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.

摘要翻译： 非易失性存储器件包括分别形成在第一布线（11）与第二布线（14）交叉的横截面处的通孔（12），以及各自包括电流控制层（13b）的电流控制元件（13），第一电极层 （13a）和第二电极层（13c），使得电流控制层（13b）夹在第一电极层（13a）和第二电极层（13c）之间，其中电阻可变元件（15）设置在其内 通孔（12）分别设置成覆盖通孔（12），电流控制层（13b）被设置成覆盖第一电极层（13a）， 第二电极层（13c）设置在电流控制层（13b）上，第二导线的导线层（14a）设置在第二电极层（13c）上，第二导线（14）各自包括电流 控制层（13b），第二电极层（13c）和第二wi的导线层（14a） 回覆。

公开(公告)号：US20100193760A1

公开(公告)日：2010-08-05

申请号：US12669174

申请日：2008-07-11

申请人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： H01L45/00 ,  H01L27/04 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

摘要翻译： 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

公开(公告)号：US20100090193A1

公开(公告)日：2010-04-15

申请号：US12445380

申请日：2007-10-12

申请人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

发明人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

摘要翻译： 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29）以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

公开(公告)号：US07679744B2

公开(公告)日：2010-03-16

申请号：US11987714

申请日：2007-12-04

申请人： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

发明人： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

IPC分类号： G01J4/00

CPC分类号： G01J4/00

摘要： The invention provides a Stokes parameter measurement device and Stokes parameter measurement method that enable high-precision measurement. The Stokes parameter measurement device comprises a polarization splitting device which comprises an optical element formed of a birefringent crystal material and which, by means of the optical element, splits signal light to be measured into a plurality of polarized light beams and adjusts the polarization state of one or more among the plurality of polarized light beams, and a light-receiving portion for performing photoelectric conversion of an optical component of the signal light split by and emitted from the polarization splitting device.

摘要翻译： 本发明提供了能够进行高精度测量的斯托克斯参数测量装置和斯托克斯参数测量方法。 斯托克斯参数测量装置包括偏振分离装置，其包括由双折射晶体材料形成的光学元件，并且通过光学元件将待测量的信号光分解为多个偏振光束并调节偏振态 多个偏振光束中的一个或多个，以及用于对由偏振分离装置分离和发射的信号光的光学分量执行光电转换的光接收部分。

公开(公告)号：US20100051892A1

公开(公告)日：2010-03-04

申请号：US12446964

申请日：2007-10-22

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： H01L47/00 ,  H01L21/16

CPC分类号： H01L27/101 ,  H01L27/24

摘要： A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a semiconductor substrate (11), an active element forming region provided on the semiconductor substrate (11) and including a plurality of active elements (12), a wire forming region which is provided on the active element forming region to electrically connect the active elements (12) and includes plural layers of semiconductor electrode wires (15, 16), a memory portion forming region (100) which is provided above the wire forming region and provided with memory portions (26) arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, and an oxygen barrier layer (17) which is provided between the memory portion forming region (100) and the wire forming region so as to extend continuously over at least an entire of the memory portion forming region (100).

摘要翻译： 本发明的非易失性半导体存储器件（10）包括半导体衬底（11），设置在半导体衬底（11）上并包括多个有源元件（12）的有源元件形成区域， 设置在有源元件形成区域上以电连接有源元件（12）并且包括多层半导体电极线（15,16），存储部形成区域（100），其设置在线形成区域的上方并设置有存储器 布置成矩阵的部分（26），每个存储部分的电阻值根据施加的电脉冲而变化，以及设置在存储部分形成区域（100）和线形成区域之间的氧阻挡层（17），从而 以在至少整个存储部分形成区域（100）上连续地延伸。

公开(公告)号：US20090283736A1

公开(公告)日：2009-11-19

申请号：US12307211

申请日：2008-03-26

申请人： Yoshihiko Kanzawa ,  Koji Katayama ,  Satoru Fujii ,  Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Ryoko Miyanaga ,  Takeshi Takagi ,  Kazuhlko Shimakawa

发明人： Yoshihiko Kanzawa ,  Koji Katayama ,  Satoru Fujii ,  Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Ryoko Miyanaga ,  Takeshi Takagi ,  Kazuhlko Shimakawa

IPC分类号： H01L45/00 ,  H01L21/16 ,  H01L29/12

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/90

摘要： A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0

摘要翻译： 非易失性存储元件包括设置在第一电极层（103）和第二电极层（107）之间的第一电极层（103），第二电极（107）和电阻变化层（106），电阻 电阻变化层的值根据施加在电极（103），（107）之间的具有不同极性的电信号而可逆地变化，其中电阻变化层（106）具有第一区域，该第一区域包括第一氧缺陷型氧化钽， 由TaOx（0

公开(公告)号：US07586130B2

公开(公告)日：2009-09-08

申请号：US11344574

申请日：2006-02-01

申请人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

发明人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

IPC分类号： H01L29/732

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78642 ,  Y10S977/938

摘要： A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.

摘要翻译： 垂直场效应晶体管包括：具有用作沟道区的线性结构束的有源区; 用作源极和漏极区之一的下电极; 上电极，用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。 晶体管还包括在上电极和下电极之间的电介质部分。 上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方横向突出的突出部分。 有源区域位于上电极的伸出部分正下方。

公开(公告)号：US07564073B2

公开(公告)日：2009-07-21

申请号：US11294566

申请日：2005-12-06

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L27/04

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20070052041A1

公开(公告)日：2007-03-08

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由所述连接部的至少一部分在所述连接部的长度方向上形成的通路区域（15a） 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US07084026B2

公开(公告)日：2006-08-01

申请号：US10913383

申请日：2004-08-09

申请人： Takeshi Takagi ,  Akira Inoue

发明人： Takeshi Takagi ,  Akira Inoue

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/802 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/78687

摘要： A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe layer 17 are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer 17 located between the source and drain regions 19 and 20 are an Si buffer region 22 and an SiGe channel region 23, respectively, which contain the n-type impurity of low concentration. A region of an Si film 18 located directly under a gate insulating film 12 is an Si cap region 24 into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.

摘要翻译： 位于源区和漏区19和20之间的Si层15的区域是含有高浓度的n型杂质的Si体区21。 处于生长状态的Si层16和SiGe层17未掺杂n型杂质的未掺杂层。 位于源区和漏区19和20之间的Si层16和SiGe层17的区域分别是含有低浓度的n型杂质的Si缓冲区22和SiGe沟道区23。 位于栅极绝缘膜12正下方的Si膜18的区域是Si帽区域24，其中p型杂质（5×10 17原子％-3重量％ ）掺杂。 因此，可以实现抑制阈值电压增加的半导体装置。