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公开(公告)号：US20210271402A1
公开(公告)日：2021-09-02
申请号：US17324121
申请日：2021-05-19
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US10824354B2
公开(公告)日：2020-11-03
申请号：US16686200
申请日：2019-11-17
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US10783071B2
公开(公告)日：2020-09-22
申请号：US16197034
申请日：2018-11-20
Applicant: Silicon Motion, Inc.
Inventor： Ting-Hsing Wang , Yang-Chih Shen
Abstract: A data storage device with a non-volatile memory on which a garbage collection operation is segmented to be accomplished at separate time intervals. Host commands are inserted to be executed between the separate time intervals. A data swap stage or/and an F2H table update stage or/and an H2F table update stage for a garbage collection operation may be segmented to be performed at separate time intervals.
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公开(公告)号：US10521142B2
公开(公告)日：2019-12-31
申请号：US16260142
申请日：2019-01-29
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US20190155531A1
公开(公告)日：2019-05-23
申请号：US16260142
申请日：2019-01-29
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G06F2212/7206 , G11C11/5628 , G11C11/5642 , Y02D10/13
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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Patent Agency Ranking
公开(公告)号：US10283216B2
公开(公告)日：2019-05-07
申请号：US15649394
申请日：2017-07-13
Applicant: Silicon Motion, Inc.
Inventor： Ching-Ke Chen , Po-Sheng Chou , Yang-Chih Shen
Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read.
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27.发明授权Methods for accessing a storage unit of a flash memory and apparatuses using the same 有权访问闪速存储器的存储单元的方法和使用其的装置公开(公告)号：US09411686B2
公开(公告)日：2016-08-09
申请号：US14331591
申请日：2014-07-15
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Yang-Chih Shen , Sheng-I Hsu
CPC classification number: G06F11/108 , G06F11/1012 , G06F2211/109
Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.
Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在RAID（独立磁盘冗余阵列）组中的所有消息被编程之后，确定是否已经生成RAID组内的垂直ECC（纠错码）。 处理单元引导DMA（直接存储器访问）控制器从DRAM（动态随机存取存储器）获得垂直ECC，并且当生成RAID组内的垂直ECC时，将垂直ECC存储到缓冲器，从而使垂直 ECC被编程到存储单元。
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28.发明申请公开(公告)号：US20160132249A1
公开(公告)日：2016-05-12
申请号：US14996846
申请日：2016-01-15
Applicant: Silicon Motion, Inc.
Inventor： Yang-Chih Shen
IPC: G06F3/06
CPC classification number: G06F3/0604 , G06F3/0629 , G06F3/0685 , G06F11/10 , G06F11/1012 , G06F11/1072 , G06F11/1076 , G06F11/108 , G06F13/16 , G06F13/28 , G06F2212/7208 , G11C11/5628 , G11C14/0018 , G11C16/3427 , G11C2029/0411
Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A storage-unit access interface is directed to program data into the nth wordline of a storage unit. The storage-unit access interface is directed to program the same data into the (n−1)th wordline of the storage unit after the storage unit completes the data programming of the nth wordline of the storage unit. The storage-unit access interface is directed to program the same data into the (n−2)th wordline of the storage unit after the storage unit completes the data programming of the (n−1)th wordline of the storage unit, where n is an integer greater than 2.
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29.发明申请公开(公告)号：US20160062908A1
公开(公告)日：2016-03-03
申请号：US14738500
申请日：2015-06-12
Applicant: Silicon Motion, Inc.
Inventor： Yang-Chih Shen , Hou-Yun Lee
CPC classification number: G06F12/0246 , G06F2212/1016 , G06F2212/7201 , G11C7/1072
Abstract: A method for maintaining a storage mapping table. An access interface is directed to read a group mapping table from the last page of a block of a storage unit. The block is allocated to store data of a plurality of groups, each group stores information indicating which location in the storage unit stores data of an LBA (Logical Block Address) range, and the group mapping table stores information indicating which unit of the block stores the latest data of each group. The group mapping table is stored in a DRAM (Dynamic Random Access Memory). The access interface is directed to read data of each group from the storage unit according to the group mapping table. The data of each group is stored in a specified location of a storage mapping table of the DRAM.
Abstract translation: 一种用于维护存储映射表的方法。 访问接口用于从存储单元的块的最后一页读取组映射表。 分配该块以存储多个组的数据，每个组存储指示存储单元中的哪个位置存储LBA（逻辑块地址）范围的数据的信息，并且组映射表存储指示块的哪个单元存储的信息 每组的最新数据。 组映射表存储在DRAM（动态随机存取存储器）中。 访问接口用于根据组映射表从存储单元读取每个组的数据。 每个组的数据被存储在DRAM的存储映射表的指定位置。
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公开(公告)号：US09256529B2
公开(公告)日：2016-02-09
申请号：US14596236
申请日：2015-01-14
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G06F2212/7206 , G11C11/5628 , G11C11/5642 , Y02D10/13
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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