公开(公告)号：US20170117285A1

公开(公告)日：2017-04-27

申请号：US15290960

申请日：2016-10-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

公开(公告)号：US09431407B2

公开(公告)日：2016-08-30

申请号：US14491596

申请日：2014-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

公开(公告)号：US09293359B2

公开(公告)日：2016-03-22

申请号：US14191625

申请日：2014-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Hieu Van Tran ,  Chien-Sheng Su ,  Prateep Tuntasood

IPC: H01L29/788 ,  H01L21/762 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

Abstract translation: 一种存储器件阵列，其具有形成在半导体衬底中的间隔开的平行隔离区域，在每对相邻隔离区域之间具有有源区域。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域，其间具有通道区域，在第一沟道区域部分上的浮动栅极以及在第二沟道区域部分上的选择栅极。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的一部分向下延伸到沟槽中并且横向设置成与沟槽的侧壁相邻。

公开(公告)号：US20160043095A1

公开(公告)日：2016-02-11

申请号：US14790540

申请日：2015-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

Abstract translation: 非易失性存储单元包括在第二导电类型的衬底中的第一导电类型的第一和第二间隔开的区域的半导体衬底，以及衬底中的沟道区。 浮动栅极具有垂直设置在沟道区域的第一部分上的第一部分和垂直设置在第一区域上的第二部分。 浮动门包括倾斜的上表面，其以一个或多个尖锐边缘终止。 擦除栅极垂直设置在浮动栅极上，其中一个或多个尖锐边缘面向擦除栅极。 控制门具有横向邻近浮动栅极设置的第一部分，并且垂直地设置在第一区域上。 选择栅极具有垂直设置在沟道区域的第二部分上并且横向邻近浮置栅极的第一部分。

公开(公告)号：US20150263040A1

公开(公告)日：2015-09-17

申请号：US14216553

申请日：2014-03-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do

IPC: H01L27/12 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7841 ,  H01L29/7881

Abstract: A semiconductor device having a silicon substrate with a first area including a buried insulation layer with silicon over and under the insulation layer and a second area in which the substrate lacks buried insulation disposed under any silicon. Logic devices are formed in the first area having spaced apart source and drain regions formed in the silicon that is over the insulation layer, and a conductive gate formed over and insulated from a portion of the silicon that is over the insulation layer and between the source and drain regions. Memory cells are formed in the second area that include spaced apart second source and second drain regions formed in the substrate and defining a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region.

Abstract translation: 一种具有硅衬底的半导体器件，其具有第一区域，该第一区域包括在绝缘层之上和之下的具有硅的掩埋绝缘层，以及第二区域，其中衬底缺少设置在任何硅下的掩埋绝缘体。 逻辑器件形成在第一区域中，其中形成在绝缘层之上的硅中具有间隔开的源极和漏极区域，以及形成在绝缘层之上和源极之间的硅的一部分上并与其绝缘的导电栅极 和漏区。 存储单元形成在第二区域中，该第二区域包括形成在基板中的间隔开的第二源极和第二漏极区域，并且在其间限定沟道区域;布置在沟道区域的第一部分之上并与沟道区域的第一部分绝缘的浮置栅极;以及选择栅极 并且与沟道区域的第二部分绝缘。

公开(公告)号：US20150179749A1

公开(公告)日：2015-06-25

申请号：US14133821

申请日：2013-12-19

Applicant: Silicon Storage Technology, Inc

Inventor： Bomy Chen ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L29/423 ,  H01L29/66 ,  G11C16/10 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L29/42328 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28238 ,  H01L27/11517 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. Any portion of the trench between the pair of floating gates is free of electrically conductive elements except for a lower portion of the erase gate.

Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘，以控制其导电性。 擦除栅极至少部分地设置在浮栅上并与浮栅绝缘。 一对浮动栅极之间的沟槽的任何部分除了擦除栅极的下部以外没有导电元件。

公开(公告)号：US10714634B2

公开(公告)日：2020-07-14

申请号：US16166342

申请日：2018-10-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/49 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11524 ,  H01L27/11534 ,  H01L21/28

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

公开(公告)号：US10217850B2

公开(公告)日：2019-02-26

申请号：US15474879

申请日：2017-03-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US20170373077A1

公开(公告)日：2017-12-28

申请号：US15701357

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

公开(公告)号：US09793280B2

公开(公告)日：2017-10-17

申请号：US15057590

申请日：2016-03-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Man-Tang Wu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11534 ,  G11C16/04

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.