公开(公告)号：US06628539B2

公开(公告)日：2003-09-30

申请号：US09872975

申请日：2001-05-31

Applicant: Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

Inventor： Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

IPC: G11C1900

CPC classification number: G11C11/419 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30141

Abstract: A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

公开(公告)号：US06369616B1

公开(公告)日：2002-04-09

申请号：US09599050

申请日：2000-06-21

Applicant: Jiann-Cherng James Lan ,  Sudarshan Kumar

Inventor： Jiann-Cherng James Lan ,  Sudarshan Kumar

IPC: H03K19096

CPC classification number: H03K19/1731

Abstract: A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. The shared pull-up transistor may be used to precharge an output node of the circuit. This circuit may be found useful in clock buffering applications.

Abstract translation: 第一上拉晶体管具有耦合到时钟信号线的栅极和耦合到第一下拉晶体管和电压钳两者的漏极。 第二上拉晶体管具有还耦合到时钟信号线的栅极和耦合到第二下拉晶体管和电压钳两者的漏极。 共享上拉晶体管具有也耦合到时钟信号线的栅极和耦合到第一和第二下拉晶体管的漏极。 共享上拉晶体管可以用于对电路的输出节点进行预充电。 该电路可用于时钟缓冲应用。

公开(公告)号：US06351151B2

公开(公告)日：2002-02-26

申请号：US09909104

申请日：2001-07-18

Applicant: Sudarshan Kumar ,  Wenjie Jiang

Inventor： Sudarshan Kumar ,  Wenjie Jiang

IPC: H03K19096

CPC classification number: H03K19/00338 ,  H03K19/096

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract translation: 一种降低动态电路软错误的技术。 对于一个实施例，动态电路包括具有输出节点的动态逻辑门，在该输出节点检测逻辑门的逻辑输出值。 耦合到输出节点的保持器电路被配置为通过增加输出节点处的临界电荷来硬化动态电路。

公开(公告)号：US5944777A

公开(公告)日：1999-08-31

申请号：US851527

申请日：1997-05-05

Applicant: Sanjay Kumar ,  Sudarshan Kumar

Inventor： Sanjay Kumar ,  Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/508

CPC classification number: G06F7/508

Abstract: An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first logic level, and the second group of group generate terms are combined to calculate a second result at the same logic level. The first and second results are then combined to calculate a carry-out at a second logic level.

Abstract translation: 用于产生进位的加法器电路和由加法器电路实现的方法。 计算第一组和第二组连续组生成项。 将组的第一组生成术语组合以计算第一逻辑电平的第一结果，并且组合第二组组生成术语以在相同逻辑电平处计算第二结果。 然后组合第一和第二结果以在第二逻辑电平计算进位输出。

公开(公告)号：US5900744A

公开(公告)日：1999-05-04

申请号：US774431

申请日：1996-12-30

Applicant: Bharat K. Bisen ,  Sudarshan Kumar

Inventor： Bharat K. Bisen ,  Sudarshan Kumar

IPC: H03K19/094 ,  H03K19/02 ,  H03K19/096

CPC classification number: H03K19/09429

Abstract: A method and apparatus for providing a high speed tristate buffer. The buffer includes a p-channel pull-up transistor and a transfer gate. The source of the transistor is coupled to a voltage supply. The drain of the transistor is coupled to the buffer output. The gate of the transfer gate is coupled to a first clock source. The input to the transfer gate is a second clock source, and the output of the transfer gate is coupled to the gate of the p-channel transistor.

Abstract translation: 一种用于提供高速三态缓冲器的方法和装置。 该缓冲器包括一个p沟道上拉晶体管和一个传输门。 晶体管的源极耦合到电压源。 晶体管的漏极耦合到缓冲器输出端。 传输门的栅极耦合到第一时钟源。 传输门的输入是第二个时钟源，传输门的输出耦合到p沟道晶体管的栅极。

公开(公告)号：US5889693A

公开(公告)日：1999-03-30

申请号：US851220

申请日：1997-05-05

Applicant: Vivek Joshi ,  Sudarshan Kumar

Inventor： Vivek Joshi ,  Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/505 ,  G06K7/50

CPC classification number: G06F7/5055 ,  G06F7/507

Abstract: A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, thereby producing a second number. The number of least significant bits extracted is determined by the incrementing value. The incrementing unit further includes an adjusting unit for adding an adjusting value to the least significant bits extracted from the first number, thereby producing an adjusted least significant bits. The incrementing unit further includes an incrementor block for receiving the second number and incrementing the second number, thereby producing a fourth number. The the extract/restore unit further for restoring the adjusted least significant bits to the fourth number, thereby producing a final result.

Abstract translation: 提供了一种CMOS反相器的方法和装置，用于将第一数量增加一个，三个或两个倍数。 递增单元包括用于从第一数量提取多个最低有效位的提取/恢复单元，从而产生第二数量。 提取的最低有效位的数量由递增值确定。 增量单元还包括调整单元，用于将调整值与从第一数量提取的最低有效位相加，从而产生经调整的最低有效位。 递增单元还包括用于接收第二数量并递增第二数量的增量块，从而产生第四数。 所述提取/还原单元还用于将经调整的最低有效位恢复到第四数，从而产生最终结果。

公开(公告)号：US20220012304A1

公开(公告)日：2022-01-13

申请号：US17369801

申请日：2021-07-07

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G06F17/16 ,  G06F5/01 ,  G06F7/544

Abstract: A system and method of multiplying a first matrix and a second matrix is provided, the method comprising compressing the second matrix into a third matrix to process primarily non-zero values. For each row in the first matrix, a row may be loaded into a row lookup unit. For each entry in the third matrix, a row address may be extracted, a row value may be obtained from a corresponding loaded row of the first matrix based on the extracted row address, the row value from the loaded row may be multiplied with the matrix value from the third matrix for each column, and the multiplied value may be added to an accumulator corresponding to the each column. Lastly, a multiplied matrix may be output for the loaded row.

公开(公告)号：US06833735B2

公开(公告)日：2004-12-21

申请号：US10335141

申请日：2002-12-31

Applicant: Sudarshan Kumar ,  Jiann-Cherng Lan ,  Snehal Jariwala ,  Wenjie Jiang

Inventor： Sudarshan Kumar ,  Jiann-Cherng Lan ,  Snehal Jariwala ,  Wenjie Jiang

IPC: H03K19096

CPC classification number: H03K19/0963

Abstract: A complementary metal oxide semiconductor (CMOS) low-power, high speed logic circuit consisting of a cascaded chain of stages. The first stage is a pulsed domino logic circuit having one or more logic signal inputs for receiving data signals, and a timing input for receiving a clocking pulse that conditions the input pulse domino stage for evaluation during a brief window of time. The output of the pulsed domino circuit is connected to a chain of series-connected skewed static logic gates, each having the channel sizes of its pull-up and pull-down transistors ratioed to a produce, from gate-to-gate in the static logic chain, alternating fast high-to-low and low-to-high transitions for the information carrying leading edge of said input data signals. The use of a pulsed domino first stage driving a chain of skewed logic static gates reduces power consumption but retains the speed of conventional domino logic circuits.

Abstract translation: 一种互补的金属氧化物半导体（CMOS）低功耗高速逻辑电路，由级联的级联链组成。 第一级是具有用于接收数据信号的一个或多个逻辑信号输入的脉冲多米诺逻辑电路，以及用于接收时钟脉冲的定时输入，用于在简短的时间窗口期间控制输入脉冲多米诺骨架级以进行评估。 脉冲多米诺骨电路的输出连接到串联连接的偏斜静态逻辑门，每条链的上拉和下拉晶体管的沟道尺寸与产品的栅极到栅极的静态 逻辑链，用于传送所述输入数据信号前沿的信息的交替快速高到低和从低到高的转变。 使用脉冲多米诺骨牌第一阶段驱动偏斜逻辑静态门链降低了功耗，但保留了常规多米诺逻辑电路的速度。

公开(公告)号：US06820106B1

公开(公告)日：2004-11-16

申请号：US09604620

申请日：2000-06-27

Applicant: Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

Inventor： Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

IPC: G06F738

CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49957 ,  G06F7/74

Abstract: A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generator in parallel. A rounding control unit is coupled to the LZA and coupled to a multiplexor that outputs a result from one of the adder, the plus-oner, and the plus-two-er responsive to the rounding control unit. A normalization shifter is coupled to the multiplexor and the LZA.

Abstract translation: 一种提高浮点乘法器累加器（FMAC）性能的方法和装置。 该方法包括接收三个浮点数并计算第一个浮点数和第二个浮点数的乘积，并加上第三个浮点数以产生一个和值和一个进位值。 然后根据和值和进位值计算传播值，杀死值和生成值。 同时将总和值加到进位值以创建第一个结果，将和值添加到进位值并递增1以创建第二个结果，将总和值添加到进位值并递增2以创建 确定第三结果和小数点位置。 然后根据舍入模式和小数点位置选择第一个结果之一，第二个结果和第三个结果。 所选结果根据小数点位置进行归一化。 该装置包括具有耦合到其的传播，杀死，生成发生器（PKG发生器）的乘法器。 加法器，加法器，加二和前导零预测器（LZA）均并联耦合到PKG发生器。 四舍五入控制单元耦合到LZA，并且耦合到多路复用器，该多路复用器响应于舍入控制单元输出加法器，加上器和加二乘法器中的一个的结果。 归一化移位器耦合到多路复用器和LZA。

公开(公告)号：US06629194B2

公开(公告)日：2003-09-30

申请号：US09872965

申请日：2001-05-31

Applicant: Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

Inventor： Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

IPC: G06F1200

CPC classification number: G06F9/30141 ,  G06F9/3012 ,  G11C7/12 ,  G11C2207/007 ,  G11C2207/2281

Abstract: A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.