公开(公告)号：US07675783B2

公开(公告)日：2010-03-09

申请号：US12035732

申请日：2008-02-22

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

摘要： Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

摘要翻译： 提供一种非易失性存储装置及其驱动方法。 在驱动非易失性存储器件的方法中，确定要驱动的存储单元的结构形状和位置，然后使用确定结果根据存储单元的分布以优化的操作条件驱动存储单元。

公开(公告)号：US07633096B2

公开(公告)日：2009-12-15

申请号：US11461681

申请日：2006-08-01

申请人： Ki-Whan Song ,  Yeong-Taek Lee

发明人： Ki-Whan Song ,  Yeong-Taek Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0262

摘要： A Silicon-Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) protection includes an isolation device. The isolation device isolates a main ground voltage line, connected to a first cathode, from a peripheral ground voltage line, connected to a second cathode. As result, even when noise occurs in the peripheral ground voltage line during the operation of an integrated circuit, the main ground voltage line maintains a stable voltage level.

摘要翻译： 用于静电放电（ESD）保护的硅控整流器（SCR）包括隔离装置。 隔离装置将连接到第一阴极的主接地电压线与连接到第二阴极的外围接地电压线隔离。 因此，即使在集成电路的动作中，外围接地电压线发生噪声时，主接地电压线保持稳定的电压电平。

公开(公告)号：US07551480B2

公开(公告)日：2009-06-23

申请号：US11637791

申请日：2006-12-13

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0408 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

摘要： A flash memory device comprises a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

摘要翻译： 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。

公开(公告)号：US20080094914A1

公开(公告)日：2008-04-24

申请号：US11616411

申请日：2006-12-27

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/3495

摘要： Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

摘要翻译： 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

公开(公告)号：US07359245B2

公开(公告)日：2008-04-15

申请号：US11250720

申请日：2005-10-14

申请人： Dong-Hwan Kim ,  Yeong-Taek Lee

发明人： Dong-Hwan Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

摘要： There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

摘要翻译： 提供了一种具有多电平单元的闪存器件及其读取和编程方法。 具有多电平单元的闪速存储器件包括存储单元阵列，用于对位线进行预充电的单元，用于向位线提供电压的位线电压供应电路，以及每个都执行与位线不同的功能的第一至第三锁存电路 彼此。 读取和编程方法由LSB和MSB读取和编程操作执行。 通过读取LSB两次并通过读取MSB一次来实现存储器件中的读取方法。 通过编程LSB一次并编程MSB一次来实现编程方法。 具有多级数据的数据可以通过两次编程操作被编程到存储器单元中。

公开(公告)号：US07173861B2

公开(公告)日：2007-02-06

申请号：US10977703

申请日：2004-10-28

申请人： Hyun-Chul Cho ,  Yeong-Taek Lee

发明人： Hyun-Chul Cho ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/24

摘要： According to some embodiments, a nonvolatile semiconductor memory device includes high voltage circuits that prevent high voltages, which are applied to bitlines during an erase operation, from being applied to low voltage circuits that are operable with low voltages. Each high voltage circuit includes a first switching circuit for selectively isolating the low voltage circuit from the bitlines, and a second switching circuit for inhibiting a leakage current to the low voltage circuit from the bitlines. The second switching circuit is connected between the first switching circuit and the low voltage circuit.

摘要翻译： 根据一些实施例，非易失性半导体存储器件包括防止在擦除操作期间施加到位线的高电压被施加到可以以低电压操作的低电压电路的高压电路。 每个高压电路包括用于选择性地将低压电路与位线隔离的第一开关电路和用于抑制从位线到低压电路的漏电流的第二开关电路。 第二开关电路连接在第一开关电路和低电压电路之间。

公开(公告)号：US20060215472A1

公开(公告)日：2006-09-28

申请号：US11300009

申请日：2005-12-13

申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Yeong-Taek Lee ,  Chul Lee

发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Yeong-Taek Lee ,  Chul Lee

IPC分类号： G11C7/02

CPC分类号： G11C11/4097 ,  G11C2207/005

摘要： Provided is a memory device with a shared open bit line sense amplifier architecture. The memory device includes memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.

摘要翻译： 提供了具有共享开放位线读出放大器架构的存储器件。 存储器件包括存储器单元阵列，每个存储单元阵列包括位线，以及读出放大器，配置为将至少两个位线耦合到存储单元阵列并被配置为耦合到不同存储单元阵列的至少两个位线。

公开(公告)号：US20060140002A1

公开(公告)日：2006-06-29

申请号：US11356620

申请日：2006-02-17

申请人： Dong-Hwan Kim ,  Yeong-Taek Lee

发明人： Dong-Hwan Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

摘要： There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

公开(公告)号：US06965964B2

公开(公告)日：2005-11-15

申请号：US10340359

申请日：2003-01-09

申请人： Yeong-Taek Lee ,  Kang-Deog Suh

发明人： Yeong-Taek Lee ,  Kang-Deog Suh

IPC分类号： G11C16/06 ,  G11C7/10 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  G06F12/00

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C16/0483 ,  G11C16/32 ,  G11C2216/14

摘要： A NAND flash memory device is provided. The memory device includes M input/output pins for inputting and outputting M-bit data (M is any natural number), first and second input buffer circuits, an address register, a command register, and a data input register. The first and second input buffer circuits receive N least significant bits (N is any natural number) and N most significant bits, respectively, of the M-bit data inputted via the input/output pins. The address register receives as an address an output of the first input buffer circuit in response to address load signals. The command register receives as a command an output of the first address buffer circuit in response to the command load signal. The data input register simultaneously receives outputs of the first and second input buffer circuits in response to the data load signal, as data to be programmed. The M-bit data latched in the data input register is loaded on the sense and latch block via a data bus. According to these configurations of the NAND flash memory device, at each of modes of operation where a command, an address, and data are serially received, the data is inputted and outputted through all of the M input/output pins, while each of the command and the address is inputted through N least significant bit input/output pins.

摘要翻译： 提供NAND闪速存储器件。 存储器件包括用于输入和输出M位数据（M是任意自然数）的M个输入/输出引脚，第一和第二输入缓冲电路，地址寄存器，命令寄存器和数据输入寄存器。 第一和第二输入缓冲电路分别经由输入/输出引脚输入的M位数据分别接收N个最低有效位（N为任意自然数）和N个最高有效位。 地址寄存器响应地址负载信号接收第一输入缓冲电路的输出作为地址。 命令寄存器响应于命令负载信号，作为命令接收第一地址缓冲器电路的输出。 数据输入寄存器同时接收第一和第二输入缓冲器电路的响应于数据加载信号的输出，作为要被编程的数据。 锁存在数据输入寄存器中的M位数据通过数据总线加载到检测和锁存块上。 根据NAND闪存器件的这些配置，在命令，地址和数据被串行接收的每个操作模式下，通过所有M个输入/输出引脚输入和输出数据， 命令，并通过N个最低有效位输入/输出引脚输入地址。

公开(公告)号：US20050018488A1

公开(公告)日：2005-01-27

申请号：US10888944

申请日：2004-07-08

申请人： Dong-Hwan Kim ,  Yeong-Taek Lee

发明人： Dong-Hwan Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/30 ,  G11C11/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

摘要： There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

摘要翻译： 提供了一种具有多电平单元的闪存器件及其读取和编程方法。 具有多电平单元的闪速存储器件包括存储单元阵列，用于对位线进行预充电的单元，用于向位线提供电压的位线电压供应电路，以及每一个执行与位线不同的功能的第一至第三锁存电路 彼此。 读取和编程方法由LSB和MSB读取和编程操作执行。 通过读取LSB两次并通过读取MSB一次来实现存储器件中的读取方法。 通过编程LSB一次并编程MSB一次来实现编程方法。 具有多级数据的数据可以通过两次编程操作被编程到存储器单元中。