公开(公告)号：US11610914B2

公开(公告)日：2023-03-21

申请号：US17161504

申请日：2021-01-28

Applicant: Sunrise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L29/04

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US11515432B2

公开(公告)日：2022-11-29

申请号：US17155673

申请日：2021-01-22

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L21/8239 ,  H01L29/792 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/423

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

公开(公告)号：US20220328518A1

公开(公告)日：2022-10-13

申请号：US17809535

申请日：2022-06-28

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Wu-Yi Henry Chien ,  Jie Zhou ,  Eli Harari

IPC: H01L27/11582 ,  H01L29/66 ,  H01L21/308

Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

公开(公告)号：US20220293623A1

公开(公告)日：2022-09-15

申请号：US17804986

申请日：2022-06-01

Applicant: SunRise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11573 ,  H01L27/11565 ,  H01L29/45 ,  H01L23/528 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/225 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11582

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20210313348A1

公开(公告)日：2021-10-07

申请号：US17348603

申请日：2021-06-15

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28 ,  H01L27/1157

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US20210280605A1

公开(公告)日：2021-09-09

申请号：US17329007

申请日：2021-05-24

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Chenming Hu ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/02 ,  H01L21/28

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a moncrystlline semiconductor substrate.

公开(公告)号：US11069696B2

公开(公告)日：2021-07-20

申请号：US16509282

申请日：2019-07-11

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Raul Adrian Cernea ,  George Samachisa ,  Wu-Yi Henry Chien

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/12 ,  G11C11/56 ,  H01L27/06

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.

公开(公告)号：US20210210506A1

公开(公告)日：2021-07-08

申请号：US17161504

申请日：2021-01-28

Applicant: Sunrise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20200303414A1

公开(公告)日：2020-09-24

申请号：US16894624

申请日：2020-06-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/768

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US20200258903A1

公开(公告)日：2020-08-13

申请号：US16792790

申请日：2020-02-17

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L23/00 ,  H01L21/768

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.