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    Method for fabricating thin film transistor using the mask for forming polysilicon including slit patterns deviated from each other
    21.
    发明授权
    Method for fabricating thin film transistor using the mask for forming polysilicon including slit patterns deviated from each other 有权
    使用该掩模制造薄膜晶体管的方法，用于形成包括彼此偏离的狭缝图案的多晶硅

    公开(公告)号：US07335541B2

    公开(公告)日：2008-02-26

    申请号：US10854664

    申请日：2004-05-26

    申请人： Myung-Koo Kang ,  Sook-Young Kang ,  Hyun-Jae Kim

    发明人： Myung-Koo Kang ,  Sook-Young Kang ,  Hyun-Jae Kim

    IPC分类号： H01L21/00

    CPC分类号： H01L21/0268 ,  H01L21/2026 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.

    摘要翻译： 提供了一种用于将非晶硅结晶成多晶硅的掩模。 掩模包括用于限定要被照明的区域的多个狭缝图案。 沿着纵向第一方向形成多个狭缝图案，并且掩模沿纵向第二方向移动。 第一纵向方向基本上垂直于第二纵向方向。 每个分割图案与另一个分开的图案偏离大致相同的距离。 因此，使用掩模的多晶硅生长成相对于水平和垂直方向各向同性。

    THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY
    23.
    发明申请
    THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY 有权
    薄膜晶体管和液晶显示

    公开(公告)号：US20070108447A1

    公开(公告)日：2007-05-17

    申请号：US11621277

    申请日：2007-01-09

    申请人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

    发明人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

    IPC分类号： H01L29/76 ,  H01L29/10 ,  H01L31/036 ,  H01L31/112

    CPC分类号： H01L29/42384 ,  G02F1/13454 ,  G02F2202/104 ,  H01L21/02675 ,  H01L21/2026 ,  H01L29/78675

    摘要： The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed. In a liquid crystal display according to the present invention, a plurality of thin film transistors forming a data driver circuit include thin films of polycrystalline silicon formed by sequential lateral solidification, at least one portion of a gate electrode of each thin film transistor extends in a direction crossing the grain growing direction, and at least one of the plurality of thin film transistors has a gate electrode having a pattern different from other thin film transistors.

    摘要翻译： 本发明涉及薄膜晶体管和液晶显示器。 栅电极被形成为包括沿垂直于增益生长方向的方向延伸的至少一个部分，以使TFT的电荷迁移率均匀，而不增加驱动电路的尺寸。 根据本发明的薄膜晶体管包括在绝缘基板上具有含有生长晶粒的多晶硅薄膜的半导体图案。 半导体图案包括沟道区和相对于沟道区相反的源极和漏极区。 栅极绝缘层覆盖半导体图案。 在栅极绝缘层上形成栅电极，该栅电极具有沿与晶粒的生长方向交叉的方向延伸的至少一部分，与沟道区重叠。 在根据本发明的液晶显示器中，形成数据驱动电路的多个薄膜晶体管包括通过顺序横向固化形成的多晶硅薄膜，每个薄膜晶体管的栅电极的至少一部分以 方向与晶粒生长方向交叉，并且多个薄膜晶体管中的至少一个具有与其它薄膜晶体管不同的图案的栅电极。

    Polycrystalline silicon thin film transistor of liquid crystal display and manufacturing method thereof
    25.
    发明授权
    Polycrystalline silicon thin film transistor of liquid crystal display and manufacturing method thereof 有权
    液晶显示器的多晶硅薄膜晶体管及其制造方法

    公开(公告)号：US06822703B2

    公开(公告)日：2004-11-23

    申请号：US10128330

    申请日：2002-04-24

    申请人： Chang-Won Hwang ,  Woo-Suk Chung ,  Tae-Hyeong Park ,  Hyun-Jae Kim ,  Gyu-Sun Moon ,  Sook-Young Kang

    发明人： Chang-Won Hwang ,  Woo-Suk Chung ,  Tae-Hyeong Park ,  Hyun-Jae Kim ,  Gyu-Sun Moon ,  Sook-Young Kang

    IPC分类号： G02F1136

    CPC分类号： H01L27/1288 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214

    摘要： A polycrystalline silicon TFT for an LCD and a manufacturing method thereof is disclosed. The TFT comprises an active pattern formed on a substrate, a gate insulating layer formed on the substrate including the active pattern, a gate line formed on the gate insulating layer to be crossed with the active pattern and including a gate electrode for defining the first impurity region, a second impurity region and a channel region, an insulating interlayer formed on the gate insulating layer including the gate line, a data line formed on the insulating interlayer and connected to the second impurity region through the first contact hole which is formed through the gate insulating layer and the insulating interlayer on the second impurity region and a pixel electrode formed on the same insulating interlayer as the data line and connected with the first impurity region through a second contact hole which is formed through the gate insulating layer and the insulating interlayer on the first impurity region. The number of mask can be reduced to 5 or 6 sheets, thereby simplifying a manufacturing process.

    摘要翻译： 公开了一种用于LCD的多晶硅TFT及其制造方法。 TFT包括形成在基板上的有源图案，形成在包括有源图案的基板上的栅极绝缘层，形成在栅极绝缘层上以与有源图案交叉的栅极线，并且包括用于限定第一杂质的栅电极 区域，第二杂质区域和沟道区域，在包括栅极线的栅极绝缘层上形成的绝缘夹层，形成在绝缘层间并通过第一接触孔连接到第二杂质区域的数据线，该第一接触孔通过 栅绝缘层和第二杂质区上的绝缘中间层，以及形成在与数据线相同的绝缘夹层上的像素电极，并通过第二接触孔与第一杂质区连接，第二接触孔通过栅极绝缘层和绝缘中间层 在第一杂质区域。 掩模的数量可以减少到5张或6张，从而简化制造过程。

    Method and apparatus for determining timing for initial ranging of user equipment using ranging of adjacent pieces of user equipment in multi-hop mobile relay system
    26.
    发明授权
    Method and apparatus for determining timing for initial ranging of user equipment using ranging of adjacent pieces of user equipment in multi-hop mobile relay system 有权
    用于使用多跳移动中继系统中的相邻用户设备的测距来确定用户设备的初始测距的定时的方法和装置

    公开(公告)号：US08345589B2

    公开(公告)日：2013-01-01

    申请号：US12518246

    申请日：2007-10-31

    申请人： Hyun-Jae Kim ,  Young-Il Kim

    发明人： Hyun-Jae Kim ,  Young-Il Kim

    IPC分类号： H04B7/14

    CPC分类号： H04W56/002 ,  H04B7/2606 ,  H04W16/26 ,  H04W24/10 ,  H04W92/18

    摘要： Provided is a method and apparatus for determining timing for initial ranging of user equipment by using ranging of adjacent pieces of user equipment in a multi-hop mobile relay (MMR) system, and more particularly, a method and apparatus for determining timing for initial ranging of user equipment in which a power value and a timing value for periodic ranging of adjacent pieces of user equipment are measured so as to minimize an uplink timing error of a base station. In the MMR system, user equipment transmits an initial ranging code to the base station with irregular timing while not knowing an exact start point of an uplink of the base station. In particular, if the user equipment attempts the initial ranging at the same time as when adjacent pieces of user equipment attempt the periodic ranging and the handover ranging, an error occurs between transmission timing of the initial ranging and uplink timing, thereby acting as an inter-symbol interference (ISI) and inter-channel interference (ICI) of different ranging. As a result, the initial ranging acts as an interference signal in a ranging process of adjacent pieces of user equipment. However, the apparatus and method can minimize a timing error of the initial ranging code of user equipment by avoiding the initial ranging acting as the interference signal.

    摘要翻译： 提供了一种用于通过使用多跳移动中继（MMR）系统中的相邻用户设备的测距来确定用户设备的初始测距的定时的方法和装置，更具体地，用于确定初始测距的定时的方法和装置 测量用于相邻用户设备的周期性测距的功率值和定时值的用户设备，以使基站的上行链路定时误差最小化。 在MMR系统中，用户设备以不规则的定时向基站发送初始测距码，而不知道基站的上行链路的确切起点。 特别地，如果用户设备在相邻的用户设备尝试周期性测距和切换测距的同时尝试初始测距，则在初始测距和上行链路定时的传输定时之间出现错误， 符号干扰（ISI）和不同范围的信道间干扰（ICI）。 结果，初始测距在相邻的用户设备的测距过程中充当干扰信号。 然而，该装置和方法可以通过避免作为干扰信号的初始测距来最小化用户设备的初始测距码的定时误差。

    Methods of fabricating non-volatile memory devices including double diffused junction regions
    27.
    发明授权
    Methods of fabricating non-volatile memory devices including double diffused junction regions 有权
    制造包括双扩散连接区域的非易失性存储器件的方法

    公开(公告)号：US08324052B2

    公开(公告)日：2012-12-04

    申请号：US13010583

    申请日：2011-01-20

    申请人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    发明人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    IPC分类号： H01L21/331

    CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

    摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。

    METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS
    29.
    发明申请
    METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS 有权
    制造非易失性记忆装置的方法，包括双重扩散结区

    公开(公告)号：US20110111570A1

    公开(公告)日：2011-05-12

    申请号：US13010583

    申请日：2011-01-20

    申请人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    发明人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

    摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。