公开(公告)号：US20240347642A1

公开(公告)日：2024-10-17

申请号：US18755281

申请日：2024-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chong-De Lien ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Ming-Shuan Li ,  Hsin-Wen Su

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696 ,  H10B10/125

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

公开(公告)号：US12063768B2

公开(公告)日：2024-08-13

申请号：US18182837

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chia-Wei Chen ,  Chien-Chih Lin

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

公开(公告)号：US12063766B2

公开(公告)日：2024-08-13

申请号：US17514118

申请日：2021-10-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Chia-Hao Pao ,  Shih-Hao Lin

IPC: G11C11/412 ,  G11C11/417 ,  H01L27/092 ,  H10B10/00

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/417 ,  H01L27/092

Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.

公开(公告)号：US12040405B2

公开(公告)日：2024-07-16

申请号：US17319783

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chong-De Lien ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Ming-Shuan Li ,  Hsin-Wen Su

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696 ,  H10B10/125

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

公开(公告)号：US11728227B1

公开(公告)日：2023-08-15

申请号：US17743656

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Yi Lin ,  Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Lien-Jung Hung

IPC: H01L21/66 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884

Abstract: Test structures on a wafer are provided. A plurality of cells are arranged in rows and columns of a test array. First and second output pads are formed on opposite sides of the test array. A first output pad is coupled to the cells in one half of the rows of the test array. A second output pad is coupled to the cells in the other half of the rows of the test array. Each first input pad is coupled to the cells in respective column of the test array. Each second input pad is coupled to the cells in respective row of the test array. When a first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads, current flowing through the turned-on cell is measured through the first or second output pad.

公开(公告)号：US20230061384A1

公开(公告)日：2023-03-02

申请号：US17462709

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8234

Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.

公开(公告)号：US20230046028A1

公开(公告)日：2023-02-16

申请号：US17401151

申请日：2021-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Chih-Hsuan Chen ,  Kian-Long Lim ,  Chao-Yuan Chang ,  Feng-Ming Chang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.

公开(公告)号：US11495682B2

公开(公告)日：2022-11-08

申请号：US16802873

申请日：2020-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/267 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L27/092

Abstract: Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.

公开(公告)号：US20220344354A1

公开(公告)日：2022-10-27

申请号：US17342154

申请日：2021-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chia-Wei Chen ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L29/423 ,  H01L29/40

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

公开(公告)号：US11411100B2

公开(公告)日：2022-08-09

申请号：US17037274

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Yu-Kuan Lin ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/40 ,  H01L23/00 ,  H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L29/423 ,  H01L29/775

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.