公开(公告)号：US09627430B2

公开(公告)日：2017-04-18

申请号：US15005803

申请日：2016-01-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Chun-Chieh Chuang ,  Shuang-Ji Tsai ,  Jeng-Shyan Lin

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14636 ,  H01L27/14601 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L31/186

Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.

公开(公告)号：US20160276383A1

公开(公告)日：2016-09-22

申请号：US15167390

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Tzu-Hsuan Hsu ,  Shu-Ting Tsai ,  Min-Feng Kao

IPC: H01L27/146

CPC classification number: H01L27/1469 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Abstract translation: 公开了一种堆叠集成电路（IC）装置和方法。 堆叠的IC器件包括接合在第一半导体元件上的第一半导体元件和第二半导体元件。 第一半导体元件包括第一衬底，第一衬底中的公共导电特征，第一层间电介质（ILD）层，第一互连特征和将第一互连特征连接到公共导电特征的导电插塞。 第二半导体元件包括第二衬底，第二衬底上的第二ILD层和第二ILD层中的第二互连特征。 该装置还包括连接到第一半导体元件中的公共导电特征的导电深插头和第二互连特征。 导电深插头由第一ILD层与导电插头分开。

公开(公告)号：US20160218126A1

公开(公告)日：2016-07-28

申请号：US15090275

申请日：2016-04-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Keng-Yu Chou ,  Shuang-Ji Tsai ,  Min-Feng Kao

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  G02B1/11 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L31/02161 ,  H01L31/1868 ,  Y02E10/50 ,  Y02P70/521

Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

公开(公告)号：US09305966B2

公开(公告)日：2016-04-05

申请号：US14609066

申请日：2015-01-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Keng-Yu Chou ,  Shuang-Ji Tsai ,  Min-Feng Kao

IPC: H01L21/00 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14685 ,  G02B1/11 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L31/02161 ,  H01L31/1868 ,  Y02E10/50 ,  Y02P70/521

Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

Abstract translation: BSI图像传感器和方法。 在一个实施例中，提供具有传感器阵列和周边区域并具有前侧和后侧表面的基板; 底部抗反射涂层（BARC）在传感器阵列区域和外围区域的上方形成在第一厚度的背侧上; 在BARC上形成第一介电层; 形成金属屏蔽; 从所述传感器阵列区域上方选择性地去除所述金属屏蔽件; 从所述传感器阵列区域上方选择性地去除所述第一介电层，其中所述BARC的第一厚度的一部分也被去除，并且在选择性地去除所述第一介电层的过程中所述BARC的第一厚度的剩余部分保留; 在BARC的其余部分和金属屏蔽层之上形成第二电介质层; 以及在所述第二介电层上形成钝化层。

公开(公告)号：US09287312B2

公开(公告)日：2016-03-15

申请号：US14144121

申请日：2013-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Feng-Chi Hung ,  Shu-Ting Tsai ,  Jeng-Shyan Lin ,  Shuang-Ji Tsai ,  Wen-I Hsu

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14641

Abstract: The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a second interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first interconnect structure and second interconnect structure are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract translation: 本公开提供了用于制造三维（3D）图像传感器结构的方法的实施例。 该方法包括向其上形成有图像传感器的图像传感器基板和形成在其上的第一互连结构提供，以及形成有逻辑电路的逻辑基板和形成在其上的第二互连结构; 将逻辑基板与第一互连结构和第二互连结构夹在逻辑基板和图像传感器基板之间的结构中将逻辑基板接合到图像传感器基板; 以及形成从逻辑基板延伸到第一互连结构的导电特征，从而将逻辑电路电耦合到图像传感器。

公开(公告)号：US09245912B2

公开(公告)日：2016-01-26

申请号：US13890763

申请日：2013-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Chun-Chieh Chuang ,  Shuang-Ji Tsai ,  Jeng-Shyan Lin

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14601 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L31/186

Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.

Abstract translation: 一种用于低电阻图像传感器接触的方法和装置，所述装置包括设置在基板中的光电传感器，设置在基板的第一区域中的第一接地阱，具有比基板低的电阻的第一接地阱和地面 设置在与第一接地井相邻的区域中。 第一接地阱被配置为在衬底的第一区域中为过剩自由载流子提供从衬底到接地线的低电阻路径。 该设备可以可选地包括具有比第一接地井更低的电阻并且设置在第一接地井和接地线之间的第二接地井，并且还可以进一步可选地包括具有比第二接地井更低的电阻的第三地下井，并且设置 在第二地面井和地面线之间。

公开(公告)号：US09059061B2

公开(公告)日：2015-06-16

申请号：US14143848

申请日：2013-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Feng-Chi Hung ,  Shuang-Ji Tsai ,  Jeng-Shyan Lin ,  Shu-Ting Tsai ,  Wen-I Hsu

IPC: H01L27/14 ,  H01L27/146 ,  H01L31/02

CPC classification number: H01L27/14636 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14634 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/1469 ,  H01L31/02005

Abstract: The present disclosure provides an embodiment of an image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract translation: 本公开提供了一种图像传感器结构的实施例，其包括具有多个成像传感器的第一半导体衬底; 形成在所述第一半导体衬底上的第一互连结构; 具有逻辑电路的第二半导体衬底; 形成在所述第二半导体衬底上的第二互连结构，其中所述第一和第二半导体衬底以第一和第二互连结构夹在所述第一和第二半导体衬底之间的结构结合在一起; 以及从第一互连结构延伸到第二互连结构的背侧深度接触（BDCT）特征，从而将逻辑电路电耦合到图像传感器。

公开(公告)号：US20140264683A1

公开(公告)日：2014-09-18

申请号：US14144121

申请日：2013-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Feng-Chi Hung ,  Shu-Ting Tsai ,  Jeng-Shyan Lin ,  Shuang-Ji Tsai ,  Wen-I Hsu

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14641

Abstract: The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a first interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first and second interconnect structures are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract translation: 本公开提供了用于制造三维（3D）图像传感器结构的方法的实施例。 该方法包括向其上形成有图像传感器的图像传感器基板和形成在其上的第一互连结构提供，以及形成有逻辑电路的逻辑基板和形成在其上的第一互连结构; 将第一和第二互连结构夹在逻辑基板和图像传感器基板之间的结构中将逻辑基板接合到图像传感器基板; 以及形成从逻辑基板延伸到第一互连结构的导电特征，从而将逻辑电路电耦合到图像传感器。

公开(公告)号：US20140264682A1

公开(公告)日：2014-09-18

申请号：US13898641

申请日：2013-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Tzu-Hsuan Hsu ,  Shu-Ting Tsai ,  Min-Feng Kao

IPC: H01L23/538 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L27/1469 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Abstract translation: 公开了一种堆叠集成电路（IC）装置和方法。 堆叠的IC器件包括接合在第一半导体元件上的第一半导体元件和第二半导体元件。 第一半导体元件包括第一衬底，第一衬底中的公共导电特征，第一层间电介质（ILD）层，第一互连特征和将第一互连特征连接到公共导电特征的导电插塞。 第二半导体元件包括第二衬底，第二衬底上的第二ILD层和第二ILD层中的第二互连特征。 该装置还包括连接到第一半导体元件中的公共导电特征的导电深插头和第二互连特征。 导电深插头由第一ILD层与导电插头分开。

公开(公告)号：US20140248734A1

公开(公告)日：2014-09-04

申请号：US14271752

申请日：2014-05-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Hsiao-Hui Tseng ,  Tzu-Hsuan Hsu

IPC: H01L27/146

CPC classification number: H01L31/18 ,  H01L27/1461 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14689 ,  H01L31/02 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions.

Abstract translation: 一种方法包括形成包括第一开口的第一注入掩模，通过第一开口注入半导体衬底的第一部分以形成第一掺杂区，形成包括第二开口的第二注入掩模，以及注入半导体的第二部分 衬底以形成第二掺杂区域。 半导体衬底的第一部分被半导体衬底的第二部分包围。 注入半导体衬底的表面层以形成与第一和第二掺杂区相反导电类型的第三掺杂区。 第三掺杂区域形成具有第一和第二掺杂区域的二极管。