公开(公告)号：US20220390977A1

公开(公告)日：2022-12-08

申请号：US17833474

申请日：2022-06-06

Applicant: Texas Instruments Incorporated

Inventor： Rajat Chauhan ,  Sundeep Lakshmana Javvaji

IPC: G05F3/26

Abstract: In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. An output transistor is coupled to the first stage and to the current mirror circuit. A voltage divider network is coupled to the output transistor, and a power source is coupled to the second stage and to the voltage divider network

公开(公告)号：US20220238143A1

公开(公告)日：2022-07-28

申请号：US17537872

申请日：2021-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Divya Kaur ,  Rishav Gupta

IPC: G11C7/10 ,  H03K19/007

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

公开(公告)号：US11372032B2

公开(公告)日：2022-06-28

申请号：US15717219

申请日：2017-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Danielle Griffith ,  Per Torstein Roine ,  James Murdock ,  Bernhard Ruck

IPC: G01R19/257 ,  H03M1/66 ,  G01R31/3835

Abstract: One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.

公开(公告)号：US20210311515A1

公开(公告)日：2021-10-07

申请号：US17353387

申请日：2021-06-21

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24 ,  G05F1/59

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

公开(公告)号：US10763839B2

公开(公告)日：2020-09-01

申请号：US16357975

申请日：2019-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Srikanth Srinivasan

IPC: H03K19/094 ,  G11C16/06 ,  G11C16/12 ,  H03K5/24 ,  H03K3/356

Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

公开(公告)号：US09627035B2

公开(公告)日：2017-04-18

申请号：US15236797

申请日：2016-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prajkta Vyavahare ,  Rajat Chauhan ,  Siva Srinivas Kothamasu

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4074 ,  G06F13/10

CPC classification number: G11C11/4093 ,  G06F1/3296 ,  G06F13/102 ,  G11C7/1057 ,  G11C11/4074 ,  G11C11/4094 ,  H03K17/687 ,  Y02D10/14

Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.

公开(公告)号：US20240071539A1

公开(公告)日：2024-02-29

申请号：US18114449

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Likhita Chandrashekara ,  Yash Didhe ,  Rajat Chauhan ,  Devraj Rajagopal

IPC: G11C17/18 ,  G11C17/16 ,  H01L23/525 ,  H10B20/25

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L23/5256 ,  H10B20/25

Abstract: One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

公开(公告)号：US11914410B2

公开(公告)日：2024-02-27

申请号：US17682335

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Rajat Chauhan

IPC: G05F3/24 ,  G05F3/26 ,  H03K17/22

CPC classification number: G05F3/24 ,  G05F3/26 ,  H03K17/22

Abstract: Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.

公开(公告)号：US20230376060A1

公开(公告)日：2023-11-23

申请号：US18361978

申请日：2023-07-31

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24 ,  G05F1/59

CPC classification number: G05F1/571 ,  G05F3/24 ,  G05F1/59

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

公开(公告)号：US20230046592A1

公开(公告)日：2023-02-16

申请号：US17464261

申请日：2021-09-01

Applicant: Texas Instruments Incorporated

Inventor： Rajat Chauhan ,  Sandeep Shylaja Krishnan ,  Joseph Alan Sankman

IPC: G01R19/22 ,  H03F3/45

Abstract: In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (RDEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (RPTAT) of the differential amplifier stage, a third resistor (R1PTAT) of the scaling amplifier stage, and a fourth resistor (R2PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.