公开(公告)号：US20240312862A1

公开(公告)日：2024-09-19

申请号：US18674006

申请日：2024-05-24

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/74 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76895 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L21/743 ,  H01L23/3677 ,  H01L2224/48463

Abstract: An integrated circuit includes a semiconductor substrate. The integrated circuit also includes a trench in the semiconductor substrate, the trench including a layer of a nanoparticle material. The integrated circuit further includes an interconnect region above the trench.

公开(公告)号：US11996343B2

公开(公告)日：2024-05-28

申请号：US17114219

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/34 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L21/74

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76895 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L21/743 ,  H01L23/3677 ,  H01L2224/48463

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US10529641B2

公开(公告)日：2020-01-07

申请号：US15361390

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/373 ,  H01L23/522

Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

公开(公告)号：US10256188B2

公开(公告)日：2019-04-09

申请号：US15361401

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L27/08 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/285 ,  H01L21/324 ,  H01L21/3105 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US10069065B2

公开(公告)日：2018-09-04

申请号：US14676233

申请日：2015-04-01

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Archana Venugopal ,  Robert Reid Doering ,  Luigi Colombo

IPC: H01L43/10 ,  G01R33/07 ,  H01L43/06

Abstract: Graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

公开(公告)号：US20180151463A1

公开(公告)日：2018-05-31

申请号：US15361390

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L21/768

Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

公开(公告)号：US09517938B2

公开(公告)日：2016-12-13

申请号：US14791650

申请日：2015-07-06

Applicant: Texas Instruments Incorporated

Inventor： James Cooper Wainerdi ,  Robert Reid Doering ,  Luigi Colombo

IPC: B03C1/00 ,  C01B31/02 ,  B03C1/005 ,  B03C1/033 ,  B03C1/035 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: C01B31/0266 ,  B03C1/005 ,  B03C1/0335 ,  B03C1/035 ,  B03C2201/20 ,  B03C2201/22 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/172 ,  C01B2202/02 ,  C01B2202/22 ,  Y10S977/751 ,  Y10S977/845

Abstract: A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a dipole-inducing magnetic field which induces magnetic dipoles in the SWNTs so that a strength of a dipole depends on a conductivity of the SWNT containing the dipole, orienting the metallic SWNTs, and exposing the SWNTs to a magnetic field with a spatial gradient so that the oriented metallic SWNTs drift in the magnetic field gradient and thereby becomes spatially separated from the semiconducting SWNTs. An apparatus for the process of sorting SWNTs is disclosed.

Abstract translation: 通过将SWNTs置于稀释流体中来分离来自半导体类型的金属单壁碳纳米管（SWNT）的过程，将SWNT暴露于偶极诱导磁场，其诱导SWNT中的磁偶极子，使得偶极子的强度取决于 包含偶极子的SWNT的导电性，定向金属SWNT，并将SWNT暴露于具有空间梯度的磁场，使得定向金属SWNT在磁场梯度中漂移，从而与半导体SWNT空间分离。 公开了一种用于排序SWNT的过程的设备。

公开(公告)号：US09114995B2

公开(公告)日：2015-08-25

申请号：US14305119

申请日：2014-06-16

Applicant: Texas Instruments Incorporated

Inventor： James Cooper Wainerdi ,  Robert Reid Doering ,  Luigi Colombo

IPC: B03C1/30 ,  C01B31/02 ,  B03C1/005 ,  B03C1/033

CPC classification number: C01B31/0266 ,  B03C1/005 ,  B03C1/0335 ,  B03C1/035 ,  B03C2201/20 ,  B03C2201/22 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/172 ,  C01B2202/02 ,  C01B2202/22 ,  Y10S977/751 ,  Y10S977/845

Abstract: A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a dipole-inducing magnetic field which induces magnetic dipoles in the SWNTs so that a strength of a dipole depends on a conductivity of the SWNT containing the dipole, orienting the metallic SWNTs, and exposing the SWNTs to a magnetic field with a spatial gradient so that the oriented metallic SWNTs drift in the magnetic field gradient and thereby becomes spatially separated from the semiconducting SWNTs. An apparatus for the process of sorting SWNTs is disclosed.

Abstract translation: 通过将SWNTs置于稀释流体中来分离来自半导体类型的金属单壁碳纳米管（SWNT）的过程，将SWNT暴露于偶极诱导磁场，其诱导SWNT中的磁偶极子，使得偶极子的强度取决于 包含偶极子的SWNT的导电性，定向金属SWNT，并将SWNT暴露于具有空间梯度的磁场，使得定向金属SWNT在磁场梯度中漂移，从而与半导体SWNT空间分离。 公开了一种用于排序SWNT的过程的设备。