公开(公告)号：US20220109091A1

公开(公告)日：2022-04-07

申请号：US17495541

申请日：2021-10-06

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan Kalyani Koduri ,  Grimmett Dale Jacky

IPC: H01L33/62 ,  H01L31/0203 ,  H01L33/48 ,  H01L31/02

Abstract: An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface.

公开(公告)号：US12198995B2

公开(公告)日：2025-01-14

申请号：US18484321

申请日：2023-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan Kalyani Koduri ,  Leslie Edward Stark

IPC: H01L23/06 ,  H01L21/56 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/495

Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

公开(公告)号：US12062597B2

公开(公告)日：2024-08-13

申请号：US18297751

申请日：2023-04-10

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Sreenivasan Kalyani Koduri

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49527 ,  H01L23/49575

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

公开(公告)号：US11784103B2

公开(公告)日：2023-10-10

申请号：US17116936

申请日：2020-12-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan Kalyani Koduri ,  Leslie Edward Stark

IPC: H01L23/06 ,  H01L23/16 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/16 ,  H01L21/56 ,  H01L23/315 ,  H01L24/32 ,  H01L24/48 ,  H01L23/495 ,  H01L2224/32245 ,  H01L2224/48245

Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

公开(公告)号：US11631632B2

公开(公告)日：2023-04-18

申请号：US17135700

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Sreenivasan Kalyani Koduri

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

公开(公告)号：US11552006B2

公开(公告)日：2023-01-10

申请号：US16936290

申请日：2020-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan Kalyani Koduri

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H01L23/552 ,  H05K3/34 ,  H01L21/48

Abstract: In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.

公开(公告)号：US20220189903A1

公开(公告)日：2022-06-16

申请号：US17679087

申请日：2022-02-24

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Ralf Muenster ,  Sreenivasan Kalyani Koduri

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/15 ,  H01L23/495 ,  H01L23/373

Abstract: In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.

公开(公告)号：US11282807B2

公开(公告)日：2022-03-22

申请号：US16843559

申请日：2020-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Ralf Jakobskrueger Muenster ,  Sreenivasan Kalyani Koduri

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/15 ,  H01L23/495 ,  H01L23/373

Abstract: In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.

公开(公告)号：US20210183717A1

公开(公告)日：2021-06-17

申请号：US16859530

申请日：2020-04-27

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Sreenivasan Kalyani Koduri ,  Siva Prakash Gurrum ,  Christopher Daniel Manack

IPC: H01L23/16 ,  H01L23/00

Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.