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21.发明申请公开(公告)号：US20160330116A1
公开(公告)日：2016-11-10
申请号：US14953683
申请日：2015-11-30
Applicant: Texas Instruments Incorporated
Inventor： Tarkesh Pande , Srinivas Lingam
IPC: H04L12/721 , H04L12/741 , H04L12/26
CPC classification number: H04L45/70 , H04L43/08 , H04L43/16 , H04L45/74 , H04L47/2458
Abstract: A packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data payload. The comprises: (i) first, identifying a quality of a channel between the first node and the second node; (ii) second, in response to the quality of the channel, selecting a manner of communication of the information preceding the data payload; (iii) third, encoding the selected manner of communication in the portion of information preceding data payload; and (iv) fourth, transmitting the packet from the first node to the second node.
Abstract translation: 在第一节点和第二节点之间的分组，分组包括数据有效载荷和数据有效载荷之前的一部分信息。 包括：（i）首先，识别第一节点和第二节点之间的信道的质量; （ii）第二，响应于信道的质量，选择数据有效载荷之前的信息的通信方式; （iii）第三，在数据有效载荷之前的信息部分中对所选择的通信方式进行编码; 和（iv）第四，将分组从第一节点传送到第二节点。
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22.发明申请Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word and Non-Orthogonal Register Data File 有权具有短并行指令字和非正交寄存器数据文件的低能量加速器处理器架构公开(公告)号：US20160291974A1
公开(公告)日：2016-10-06
申请号：US14678944
申请日：2015-04-04
Inventor： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
CPC classification number: G06F9/3013 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/3877 , G06F9/3889 , G06F13/1678 , G06F13/4018 , G06F13/4022 , Y02D10/14 , Y02D10/151
Abstract: Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory ; a low energy accelerator processor configured to execute instruction words coupled to the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.
Abstract translation: 低能量加速器处理器架构的设备。 示例性布置是包括具有数据宽度N的系统总线的集成电路，其中N是正整数; 耦合到所述系统总线并被配置为执行从存储器检索的指令的中央处理器单元; 低能量加速器处理器，被配置为执行与所述系统总线耦合的指令字，并具有多个执行单元，所述多个执行单元包括加载存储单元，负载系数单元，乘法单元和蝶形/加法器ALU单元，每个执行单元 被配置为响应于检索到的指令字执行操作; 以及非正交数据寄存器文件，其包括耦合到所述多个执行单元的一组数据寄存器，所述寄存器耦合到所述多个执行单元中的所选择的执行单元。 公开了附加的方法和装置。
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公开(公告)号：US20200334197A1
公开(公告)日：2020-10-22
申请号：US16920901
申请日：2020-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
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24.发明授权公开(公告)号：US10656914B2
公开(公告)日：2020-05-19
申请号：US16545132
申请日：2019-08-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Lingam , Seok-Jun Lee , Manish Goel
Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.
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公开(公告)号：US09954514B2
公开(公告)日：2018-04-24
申请号：US14624218
申请日：2015-02-17
Applicant: Texas Instruments Incorporated
Inventor： Tarkesh Pande , Srinivas Lingam
IPC: H03H17/06
CPC classification number: H03H17/0671
Abstract: A cascaded integrator-comb filter (CIC) that includes a differentiator, a rate changer, an integrator, and a multiplier. The differentiator is configured to differentiate an input signal to produce a differentiated input signal. The rate changer is coupled to the differentiator and is configured to interpolate the differentiated input signal based on an interpolation rate to produce an upsample signal. The integrator is coupled to the rate changer and is configured to integrate the upsample signal to produce an output signal. The multiplier is coupled to the differentiator, rate changer, and integrator and is configured to increase the output signal amplitude based on the interpolation rate.
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Patent Agency Ranking
公开(公告)号：US09935681B2
公开(公告)日：2018-04-03
申请号：US15071998
申请日：2016-03-16
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Lingam , Timothy Mark Schmidl
IPC: H04B1/00 , H04B1/7097 , H04B1/709
CPC classification number: H04B1/7097 , H04B1/707 , H04B1/709 , H04L1/1671 , H04L27/2082 , H04L27/22
Abstract: A direct sequence spread spectrum (DSSS) receiver includes an antenna, signal-to-noise ratio (SNR) estimation logic, and preamble detection logic. The antenna is configured to receive a DSSS signal. The SNR estimation logic is configured to estimate SNR of the received DSSS signal. The preamble detection logic is configured to, in response to the SNR estimate exceeding a SNR threshold value, detect a preamble sequence in the DSSS signal based on an absolute value of a sequence of correlation values. The sequence of correlation values is a complex quantity.
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公开(公告)号：US20180018298A1
公开(公告)日：2018-01-18
申请号：US15714212
申请日：2017-09-25
Inventor： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
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28.发明申请公开(公告)号：US20170192751A1
公开(公告)日：2017-07-06
申请号：US14986349
申请日：2015-12-31
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Lingam , Seok-Jun Lee , Manish Goel
CPC classification number: G06F7/523 , G06F7/50 , G06F7/5324
Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.
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29.发明申请Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word 有权具有短并行指令字的低能量加速器处理器架构公开(公告)号：US20160292127A1
公开(公告)日：2016-10-06
申请号：US14678939
申请日：2015-04-04
Inventor： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
IPC: G06F15/80
CPC classification number: G06F15/80 , G06F9/30014 , G06F9/30094 , G06F9/30145 , G06F9/325 , G06F9/3822 , G06F9/3853 , G06F9/3877
Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
Abstract translation: 具有短并行指令字的低能量加速器处理器架构的方法和装置。 集成电路包括具有数据宽度N的系统总线，其中N是正整数; 耦合到所述系统总线并被配置为执行从耦合到所述系统总线的存储器检索的指令的中央处理器单元; 以及耦合到所述系统总线并被配置为执行从低能量加速器代码存储器检索的指令字的低能量加速器处理器，所述低能量加速器处理器具有多个执行单元，所述执行单元包括加载存储单元，负载系数单元，乘法 单元和蝶形/加法器ALU单元，每个执行单元被配置为响应于从检索到的指令字解码的操作码执行操作，其中指令字的宽度等于数据宽度N.附加方法和装置 被披露。
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30.发明授权Methods and apparatus for frequency offset estimation and correction prior to preamble detection of direct sequence spread spectrum (DSSS) signals 有权在直接序列扩频（DSSS）信号的前导码检测之前的频偏估计和校正的方法和装置公开(公告)号：US09231648B2
公开(公告)日：2016-01-05
申请号：US14638299
申请日：2015-03-04
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Lingam , Timothy Mark Schmidl
IPC: H04B1/7075
CPC classification number: H04B1/7075 , H04B1/7087 , H04L25/02
Abstract: Methods and apparatus for frequency offset estimation and correction prior to preamble detection of DSSS signals. An integrated circuit is disclosed including a receiver circuit having an input coupled to receive a DSSS signal, the receiver circuit configured to sample the DSSS signal and to output a sequence of digital samples; carrier frequency offset estimation logic configured to perform a carrier frequency offset estimation on the digital samples; carrier frequency correction logic configured to correct the carrier frequency of the sequence of digital samples using the carrier frequency offset estimation and to output a sequence of corrected digital samples; offset quadrature phase shift keying (O-QPSK) demodulation logic configured to perform demodulation on the corrected digital samples and further configured to output symbols corresponding to the corrected digital samples; and preamble identification configured to identify and detect a preamble sequence in the symbols. Additional methods and apparatus are disclosed.
Abstract translation: DSSS信号前导码检测前频偏估计和校正的方法和装置。 公开了一种集成电路，其包括具有耦合以接收DSSS信号的输入的接收器电路，所述接收器电路被配置为对DSSS信号进行采样并输出数字采样序列; 载波频率偏移估计逻辑，被配置为对所述数字样本执行载波频率偏移估计; 载波频率校正逻辑，被配置为使用载波频率偏移估计来校正数字样本序列的载波频率，并输出校正的数字样本序列; 偏移正交相移键控（O-QPSK）解调逻辑，被配置为对所述经校正的数字样本执行解调，并且还被配置为输出与所述经校正的数字样本相对应的符号; 以及前导码识别，被配置为识别和检测符号中的前导码序列。 公开了附加的方法和装置。
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