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    Integrated Fluxgate Device
    26.
    发明申请
    Integrated Fluxgate Device 有权

    公开(公告)号：US20210233903A1

    公开(公告)日：2021-07-29

    申请号：US17228631

    申请日：2021-04-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

    IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

    METHODS AND APPARATUS FOR SCRIBE STREET PROBE PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING
    27.
    发明申请
    METHODS AND APPARATUS FOR SCRIBE STREET PROBE PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING 有权

    公开(公告)号：US20210217706A1

    公开(公告)日：2021-07-15

    申请号：US17011982

    申请日：2020-09-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

    IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

    Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

    MULTI-PASS PLATING PROCESS WITH INTERMEDIATE RINSE AND DRY
    28.
    发明申请
    MULTI-PASS PLATING PROCESS WITH INTERMEDIATE RINSE AND DRY 审中-公开

    公开(公告)号：US20200211898A1

    公开(公告)日：2020-07-02

    申请号：US16236735

    申请日：2018-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Peter John Holverson ,  Sudtida Lavangkul

    IPC: H01L21/768 ,  H01L23/532

    Abstract: A method includes electroplate depositing a first metal layer to a first thickness on a metal seed layer, rinsing the first metal layer with deionized water, and after the first rinse process, drying the wafer. The method also includes performing one or more additional electroplating processes that respectively deposit an additional metal layer to a second thickness over the first metal layer, performing an additional rinse process that rinses the additional metal layer with deionized water, and performing an additional drying processes that dries the wafer.

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