公开(公告)号：US10447266B2

公开(公告)日：2019-10-15

申请号：US15849752

申请日：2017-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anurag Arora ,  Hariharan Nagarajan ,  Sumantra Seth

IPC: H03K19/00 ,  H04L12/12 ,  H04L12/40

Abstract: A wakeup circuit includes an amplification stage circuit and a filter stage circuit. The amplification stage circuit is configured to, in response to receiving an input signal, generate an amplified digital signal that is proportional to the input signal. The filter stage circuit is configured to, in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period (such as one clock period of a clock signal), generate a wakeup signal as an output signal of the filter stage circuit.

公开(公告)号：US10199989B2

公开(公告)日：2019-02-05

申请号：US14850531

申请日：2015-09-10

Applicant: Texas Instruments Incorporated

Inventor： Sumantra Seth ,  Ashwin Ramachandran ,  Gururaj Ghorpade

IPC: H03F1/02 ,  H03F3/30 ,  H03F3/45 ,  H03F3/72

Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

公开(公告)号：US20250086127A1

公开(公告)日：2025-03-13

申请号：US18958573

申请日：2024-11-25

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Subhashish Mukherjee

IPC: G06F13/20 ,  G06F1/08

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

公开(公告)号：US20240288893A1

公开(公告)日：2024-08-29

申请号：US18228563

申请日：2023-07-31

Applicant: Texas Instruments Incorporated

Inventor： Trilok Kamagond ,  Sumantra Seth ,  Srinivas Theertham

IPC: G05F1/575 ,  G05F1/46 ,  G05F1/565

CPC classification number: G05F1/575 ,  G05F1/468 ,  G05F1/565

Abstract: Methods, apparatus, systems, and articles of manufacture are described corresponding to a voltage regulator with frequency compensation. An example circuit includes a gain stage having a first input terminal, a second input terminal, and an output terminal; a transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal of the transistor coupled to a supply voltage terminal, the second current terminal of the transistor structured to be coupled to the second input terminal of the gain stage, and the control terminal of the transistor coupled to the output terminal of the gain stage; and regulator compensation circuitry having a first terminal and a second terminal, the first terminal of the regulator compensation circuitry coupled to the output terminal of the first gain stage, the second terminal of the regulator compensation circuitry coupled to the second input terminal of the gain stage.

公开(公告)号：US20240235480A9

公开(公告)日：2024-07-11

申请号：US17972532

申请日：2022-10-24

Applicant: Texas Instruments Incorporated

Inventor： Srikanth Manian ,  Sumantra Seth ,  Trilok Kamagond

IPC: H03F1/02 ,  H03F3/45

CPC classification number: H03F1/02 ,  H03F3/45475 ,  H03F2200/129

Abstract: A driver includes an operational amplifier which includes a first amplifier input coupled to a first driver input, a second amplifier input coupled to a second driver input, a first amplifier output, a second amplifier output, a third amplifier output and a fourth amplifier output. The first amplifier output is coupled to the first driver output and the third amplifier output is coupled to the second driver output in a voltage-mode operation. The second amplifier output is coupled to the first driver output and the fourth amplifier output is coupled to the second driver output in a current-mode operation.

公开(公告)号：US11374601B2

公开(公告)日：2022-06-28

申请号：US17200426

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Kalpesh Laxmanbhai Rajai ,  Soumyajit Roul ,  Sumantra Seth

IPC: H04B1/10 ,  H04B1/12 ,  H04B1/16 ,  H03M1/00 ,  H03M1/06 ,  H03M1/50

Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

公开(公告)号：US11296501B2

公开(公告)日：2022-04-05

申请号：US16910656

申请日：2020-06-24

Applicant: Texas Instruments Incorporated

Inventor： Alan Erik Segervall ,  Ross Anthony Pimentel ,  Sumantra Seth

IPC: H02H9/04 ,  H01L27/02 ,  H02H1/00 ,  H01L23/00

Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

公开(公告)号：US11012264B2

公开(公告)日：2021-05-18

申请号：US16701717

申请日：2019-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rama Santosh Neelim Kumar Kattamuri ,  Sumantra Seth ,  Vikram Sharma

IPC: H04L25/02 ,  H03F3/21 ,  H03F3/45 ,  H04L25/49

Abstract: A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.

公开(公告)号：US10749337B2

公开(公告)日：2020-08-18

申请号：US15808490

申请日：2017-11-09

Applicant: Texas Instruments Incorporated

Inventor： Alan Erik Segervall ,  Ross Anthony Pimentel ,  Sumantra Seth

IPC: H02H9/04 ,  H01L27/02 ,  H02H1/00 ,  H01L23/00

Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

公开(公告)号：US20180226792A1

公开(公告)日：2018-08-09

申请号：US15808490

申请日：2017-11-09

Applicant: Texas Instruments Incorporated

Inventor： Alan Erik Segervall ,  Ross Anthony Pimentel ,  Sumantra Seth

IPC: H02H9/04 ,  H01L27/02 ,  H01L23/00 ,  H02H1/00

CPC classification number: H02H9/046 ,  H01L24/05 ,  H01L24/06 ,  H01L27/0248 ,  H01L27/0259 ,  H01L27/0281 ,  H01L2224/06135 ,  H02H1/0007 ,  H02H1/0061 ,  H02H9/044

Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.