公开(公告)号：US11012264B2

公开(公告)日：2021-05-18

申请号：US16701717

申请日：2019-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rama Santosh Neelim Kumar Kattamuri ,  Sumantra Seth ,  Vikram Sharma

IPC: H04L25/02 ,  H03F3/21 ,  H03F3/45 ,  H04L25/49

Abstract: A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.

公开(公告)号：US11353943B2

公开(公告)日：2022-06-07

申请号：US16799879

申请日：2020-02-25

Applicant: Texas Instruments Incorporated

Inventor： Anurag Arora ,  Vikram Sharma ,  Sumantra Seth

IPC: G06F1/32 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26

Abstract: A wakeup circuit includes an energy detection circuit and a wakeup signal generation circuit coupled to the energy detection circuit. The energy detection circuit is configured to, in response to receiving an input signal, generate a detect signal that is proportional to the input signal. The energy detection circuit is powered by the input signal. The wakeup signal generation circuit is configured to, in response to receiving the detect signal, generate a wakeup signal.

公开(公告)号：US10700652B2

公开(公告)日：2020-06-30

申请号：US16192790

申请日：2018-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vikram Sharma ,  Gokul Koraganji

IPC: H03F3/45 ,  H04L25/02

Abstract: Some aspects of the disclosure provide for a circuit. In an example, the circuit includes an amplifier, a first transistor network, a second transistor network, a first resistor, a second resistor, and a third resistor. The amplifier has first and second inputs and first, second, third, and fourth outputs. The first transistor network is coupled to the first output of the amplifier and the second output of the amplifier. The second transistor network is coupled to the third output of the amplifier and the fourth output of the amplifier. The first resistor is coupled between the first transistor network and the second transistor network. The second resistor is coupled between the first transistor network and the first input of the amplifier. The third resistor is coupled between the second transistor network and the second input of the amplifier.

公开(公告)号：US11695539B1

公开(公告)日：2023-07-04

申请号：US17587241

申请日：2022-01-28

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Vikram Sharma ,  Shankar Ramakrishnan ,  Raghu Ganesan

IPC: H04B1/38 ,  H04L5/16 ,  H04L7/033 ,  H04L7/06 ,  H04L7/00 ,  H03K19/173 ,  H04L7/04 ,  H03K19/17784

CPC classification number: H04L7/033 ,  H03K19/1737 ,  H03K19/17784 ,  H04L7/0079 ,  H04L7/0091 ,  H04L7/048 ,  H04L7/065

Abstract: A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.