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公开(公告)号:US20200335477A1
公开(公告)日:2020-10-22
申请号:US16923115
申请日:2020-07-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Ching-Hua Hsieh , Chung-Hao Tsai , Chuei-Tang Wang , Chao-Wen Shih , Han-Ping Pu , Chien-Ling Hwang , Pei-Hsuan Lee , Tzu-Chun Tang , Yu-Ting Chiu , Jui-Chang Kuo
IPC: H01L23/00 , H01L23/538 , H01L21/768 , H01L21/48 , H01L23/66 , H01L25/00 , H01L21/56 , H01L25/065 , H01L23/31 , H01L21/683
Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
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公开(公告)号:US10756052B2
公开(公告)日:2020-08-25
申请号:US16524146
申请日:2019-07-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Ching-Hua Hsieh , Chung-Hao Tsai , Chuei-Tang Wang , Chao-Wen Shih , Han-Ping Pu , Chien-Ling Hwang , Pei-Hsuan Lee , Tzu-Chun Tang , Yu-Ting Chiu , Jui-Chang Kuo
IPC: H01L21/56 , H01L23/00 , H01L23/538 , H01L21/768 , H01L21/48 , H01L23/66 , H01L25/00 , H01L25/065 , H01L23/31 , H01L21/683 , H01L23/544
Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
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公开(公告)号:US20200091031A1
公开(公告)日:2020-03-19
申请号:US16693386
申请日:2019-11-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Chao-Wen Shih , Han-Ping Pu , Hsin-Yu Pan , Sen-Kuei Hsu
IPC: H01L23/367 , H01L23/66 , H01L23/00 , H01L21/56 , H01L21/48 , H01L23/31 , H01L23/498 , H01L21/683 , H01Q1/02 , H01Q21/08
Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.
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公开(公告)号:US10366966B1
公开(公告)日:2019-07-30
申请号:US15981929
申请日:2018-05-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Ching-Hua Hsieh , Chung-Hao Tsai , Chuei-Tang Wang , Chao-Wen Shih , Han-Ping Pu , Chien-Ling Hwang , Pei-Hsuan Lee , Tzu-Chun Tang , Yu-Ting Chiu , Jui-Chang Kuo
IPC: H01L21/56 , H01L23/00 , H01L23/538 , H01L21/768 , H01L21/48 , H01L23/66 , H01L25/00 , H01L25/065 , H01L23/31
Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
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公开(公告)号:US10157859B2
公开(公告)日:2018-12-18
申请号:US15867080
申请日:2018-01-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shou-Zen Chang , Chi-Ming Huang , Kai-Chiang Wu , Sen-Kuei Hsu , Hsin-Yu Pan , Han-Ping Pu , Albert Wan
IPC: H01L23/552 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/00
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.
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公开(公告)号:US09875972B1
公开(公告)日:2018-01-23
申请号:US15210067
申请日:2016-07-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shou-Zen Chang , Chi-Ming Huang , Kai-Chiang Wu , Sen-Kuei Hsu , Hsin-Yu Pan , Han-Ping Pu , Albert Wan
IPC: H01L23/552 , H01L23/538 , H01L23/31 , H01L25/065 , H01L21/48 , H01L21/56 , H01L25/00
CPC classification number: H01L23/552 , H01L21/485 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/3114 , H01L23/5382 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L25/0657 , H01L25/50 , H01L2225/06537 , H01L2225/06555
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.
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