公开(公告)号：US12211752B2

公开(公告)日：2025-01-28

申请号：US17660436

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin ,  Kun-Yu Lee ,  Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

公开(公告)号：US20230387246A1

公开(公告)日：2023-11-30

申请号：US18446958

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/786 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L29/4983 ,  H01L29/0673 ,  H01L29/78696 ,  H01L21/30604 ,  H01L29/66636 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/78618 ,  H01L21/02603 ,  H01L27/092

Abstract: A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.

公开(公告)号：US20230378359A1

公开(公告)日：2023-11-23

申请号：US18362210

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Shu Kuan ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/161 ,  H01L29/66803 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/1054 ,  H01L29/7834 ,  H01L29/16 ,  H01L29/66492

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

公开(公告)号：US11817499B2

公开(公告)日：2023-11-14

申请号：US17852741

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Shu Kuan ,  Cheng-Han Lee

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7834

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

公开(公告)号：US11626518B2

公开(公告)日：2023-04-11

申请号：US17121186

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/423 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/225 ,  H01L29/161

Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

公开(公告)号：US20220367715A1

公开(公告)日：2022-11-17

申请号：US17876255

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

公开(公告)号：US20220352374A1

公开(公告)日：2022-11-03

申请号：US17852741

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Shu Kuan ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

公开(公告)号：US20220246726A1

公开(公告)日：2022-08-04

申请号：US17162896

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US20220246480A1

公开(公告)日：2022-08-04

申请号：US17660436

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin ,  Kun-Yu Lee ,  Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

公开(公告)号：US11342228B2

公开(公告)日：2022-05-24

申请号：US16983527

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L29/08 ,  H01L29/165

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.