公开(公告)号：US11342228B2

公开(公告)日：2022-05-24

申请号：US16983527

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L29/08 ,  H01L29/165

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US11522086B2

公开(公告)日：2022-12-06

申请号：US17240432

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Shahaji B. More ,  Yi-Min Huang ,  Shih-Chieh Chang

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/82 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

公开(公告)号：US20210257496A1

公开(公告)日：2021-08-19

申请号：US17240432

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Shahaji B. More ,  Yi-Min Huang ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

公开(公告)号：US20220262681A1

公开(公告)日：2022-08-18

申请号：US17734521

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L29/08

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US10991826B2

公开(公告)日：2021-04-27

申请号：US16933325

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Shahaji B. More ,  Yi-Min Huang ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L21/82 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

公开(公告)号：US20200350435A1

公开(公告)日：2020-11-05

申请号：US16933325

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Shahaji B. More ,  Yi-Min Huang ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

公开(公告)号：US11776851B2

公开(公告)日：2023-10-03

申请号：US17734521

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66348 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/165

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US20230154802A1

公开(公告)日：2023-05-18

申请号：US18149495

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Han Lee ,  Chih-Yu Ma ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/0243 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/7849 ,  H01L29/7851

Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

公开(公告)号：US20230102873A1

公开(公告)日：2023-03-30

申请号：US18061031

申请日：2022-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Shahaji B. More ,  Yi-Min Huang ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

公开(公告)号：US09721826B1

公开(公告)日：2017-08-01

申请号：US15007041

申请日：2016-01-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Ma ,  Yii-Chi Lin ,  Zheng-Yang Pan ,  Chia-Chiung Lo

IPC: B23P19/04 ,  H01L21/687 ,  H01L21/67 ,  H01L21/66 ,  H01L21/324

CPC classification number: H01L21/68785 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/67248 ,  H01L21/68757 ,  H01L21/68792 ,  H01L22/20

Abstract: A wafer supporting structure in semiconductor manufacturing, and a device and a method for manufacturing semiconductor are provided. In accordance with some embodiments of the instant disclosure, a wafer supporting structure in semiconductor manufacturing includes a transparent ring and at least two arms. The arms are connected to the transparent ring.