公开(公告)号：US10283624B1

公开(公告)日：2019-05-07

申请号：US15875485

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Chi-On Chui ,  Cheng-Yu Yang ,  Yen-Ting Chen ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/762 ,  H01L21/306 ,  H01L29/417

Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

公开(公告)号：US11646311B2

公开(公告)日：2023-05-09

申请号：US16676443

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/82345 ,  H01L21/823431

Abstract: A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.

公开(公告)号：US11450569B2

公开(公告)日：2022-09-20

申请号：US17025970

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yi Lee ,  Kuan-Yu Wang ,  Cheng-Lung Hung ,  Chi-On Chui

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.

公开(公告)号：US20220216326A1

公开(公告)日：2022-07-07

申请号：US17705508

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Kai-Hsuan Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, an isolation feature over the semiconductor substrate, a fin protruding from the semiconductor substrate and through the isolation feature, a gate stack over and engaging the fin, and a gate spacer on sidewalls of the gate stack. A bottom portion of the sidewalls of the gate stack tilts inwardly towards the gate stack.

公开(公告)号：US11296084B2

公开(公告)日：2022-04-05

申请号：US16805858

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Lin ,  Chun-Heng Chen ,  Ming-Ho Lin ,  Chi-On Chui

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238

Abstract: Provided are a deposition method, a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate and a dielectric structure. The substrate includes at least one fin thereon. The dielectric structure covers the at least one fin. A thickness of the dielectric structure located on a top surface of the at least one fin is greater than a thickness of the dielectric structure located on a sidewall of the at least one fin. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is conformally disposed on the at least one fin. The second dielectric layer is disposed on the first dielectric layer over the top surface of the at least one fin. A thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

公开(公告)号：US11271113B2

公开(公告)日：2022-03-08

申请号：US16899832

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Chien-Ning Yao

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack wrapping around a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure. The semiconductor device structure includes a first inner spacer between the first portion and the stressor structure. The semiconductor device structure includes a second inner spacer between the second portion and the stressor structure.

公开(公告)号：US11195938B2

公开(公告)日：2021-12-07

申请号：US16526650

申请日：2019-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING , CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Ziwei Fang

IPC: G11C11/22 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02 ,  H01L29/423

Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.

公开(公告)号：US10833167B2

公开(公告)日：2020-11-10

申请号：US16258408

申请日：2019-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Bo-Feng Young ,  Bo-Yu Lai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/08

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.

公开(公告)号：US20200043796A1

公开(公告)日：2020-02-06

申请号：US16286558

申请日：2019-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Kai-Hsuan Lee ,  Yu-Ming Lin ,  Chi-On Chui

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/764 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L21/308

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

公开(公告)号：US10164112B2

公开(公告)日：2018-12-25

申请号：US15487559

申请日：2017-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Chi-On Chui

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311

Abstract: A semiconductor device includes a substrate; at least one source/drain feature at least partially disposed in the substrate; an isolation structure disposed on the substrate and includes a first portion; a gate structure disposed on the first portion of the isolation structure and adjacent to the source/drain feature; and at least one gate spacer disposed on a sidewall of the gate structure, in which a top surface of the first portion of the isolation structure is in contact with the gate structure and is higher than a bottommost surface of the gate spacer.