公开(公告)号：US11257827B2

公开(公告)日：2022-02-22

申请号：US16729973

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: G11C17/00 ,  H01L27/112 ,  H01L23/528 ,  G06F30/392 ,  G11C17/18 ,  H01L23/522 ,  G11C17/16

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

公开(公告)号：US20210343332A1

公开(公告)日：2021-11-04

申请号：US17186322

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Chia-En Huang

IPC: G11C11/412 ,  G11C11/417 ,  H01L27/11

Abstract: A semiconductor structure includes a substrate having a frontside and a backside; a static random-access memory (SRAM) circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells including two inverters cross-coupled together, and a first and second pass gates coupled to the two inverters; a first bit-line disposed on the frontside of the substrate and connected to the first pass gate; and a second bit-line disposed on the backside of the substrate and connected to the second pass gate.

公开(公告)号：US20210082495A1

公开(公告)日：2021-03-18

申请号：US16572625

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-En Huang ,  Hidehiro Fujiwara ,  Jui-Che Tsai ,  Yen-Huei Chen ,  Yih Wang

IPC: G11C11/419 ,  G11C11/418 ,  G11C5/06 ,  H01L27/11

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

公开(公告)号：US12048147B2

公开(公告)日：2024-07-23

申请号：US17589590

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: G11C17/00 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/528 ,  H10B20/20

CPC classification number: H10B20/20 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5226 ,  H01L23/528

Abstract: A structure includes first and second active areas, first and second gates and a data line. The first gate is continuous and crosses over the first active area and the second active area. The first gate corresponds to gate terminals of first and second transistors, and first source/drain regions of the first and the second active areas correspond to first source/drain terminals of the first and second transistors. The second gate includes first and second gate portions electrically isolated from each other. The first and second gate portions correspond to gate terminals of third and fourth transistors, respectively. The first gate portion crosses over the first active area, and the second gate portion crosses over the second active area. The first data line is coupled to the first source/drain regions of the first active area and the second active area.

公开(公告)号：US11856768B2

公开(公告)日：2023-12-26

申请号：US17750979

申请日：2022-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Chia-En Huang ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H10B41/30 ,  H01L23/522 ,  G11C7/18 ,  H01L29/872 ,  G11C8/14 ,  H10B43/30

CPC classification number: H10B41/30 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H01L29/872 ,  H10B43/30

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a Schottky diode, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate, wherein a first source/drain structure of the first transistor is electrically connected to a first source/drain structure of the second transistor. The Schottky diode is electrically connected to a gate structure of the first transistor. The first word line is electrically connected to the gate structure of the first transistor through the Schottky diode. The second word line is electrically connected to a gate structure of the second transistor. The bit line is electrically connected to a second source/drain structure of the second transistor.

公开(公告)号：US11200924B2

公开(公告)日：2021-12-14

申请号：US16876138

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Chia-En Huang ,  Yu-Hao Hsu ,  Yih Wang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

公开(公告)号：US20210366906A1

公开(公告)日：2021-11-25

申请号：US17116552

申请日：2020-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Chia-En Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L23/528

Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

公开(公告)号：US20150058664A1

公开(公告)日：2015-02-26

申请号：US13972082

申请日：2013-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Jung-Ping Yang ,  Chia-En Huang ,  Cheng Hung Lee

IPC: G06F11/10 ,  G06F11/25

CPC classification number: G06F11/25 ,  G11C29/00 ,  G11C29/808 ,  G11C29/848

Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.

Abstract translation: 存储器芯片包括具有多个存储器列的主存储器阵列，与主存储器阵列相关联的冗余存储器列，以及命中逻辑电路，其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路，用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元，以便在存储器阵列运行时由冗余存储器列进行动态替换。

公开(公告)号：US11569223B2

公开(公告)日：2023-01-31

申请号：US17086076

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Chia-En Huang

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.

公开(公告)号：US11423960B2

公开(公告)日：2022-08-23

申请号：US17085398

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/10 ,  G11C8/14 ,  G11C7/18 ,  G11C8/08 ,  G11C7/12

Abstract: A memory device is disclosed, including a first switch and multiple first memory cells that are arranged in a first column, a second switch and multiple second memory cells that are arranged in a second column, a first data line and a second data line. The first data line is coupled to the first memory cells and the second memory cells. The second data line is coupled connected to the first memory cells and the second memory cells. The first switch transmits a data signal in the first data line in response to a control signal. The second switch outputs the data signal received from the second data line in response to the control signal.