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    Bonding Structure of Dies with Dangling Bonds
    21.
    发明申请
    Bonding Structure of Dies with Dangling Bonds 有权

    公开(公告)号：US20210118832A1

    公开(公告)日：2021-04-22

    申请号：US17113357

    申请日：2020-12-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

    IPC: H01L23/00 ,  H01L23/498 ,  H03K19/1776 ,  H01L23/495

    Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

    Integrated circuit packages and methods of forming the same
    25.
    发明授权
    Integrated circuit packages and methods of forming the same 有权

    公开(公告)号：US11562982B2

    公开(公告)日：2023-01-24

    申请号：US16398159

    申请日：2019-04-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Ming-Fa Chen ,  Sung-Feng Yeh

    IPC: H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

    Semiconductor structure and manufacturing method thereof
    28.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US11094613B2

    公开(公告)日：2021-08-17

    申请号：US16547606

    申请日：2019-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Sen-Bor Jan

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector. The second connector extends further than the first connector to be in contact with a second level of the plurality of interconnecting layers between the first level of the plurality of interconnecting layers and the semiconductor substrate, and the first connector is wider than the second connector.

    Semiconductor Device and Method of Manufacture
    29.
    发明申请
    Semiconductor Device and Method of Manufacture 有权

    公开(公告)号：US20210175154A1

    公开(公告)日：2021-06-10

    申请号：US17181784

    申请日：2021-02-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66

    Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

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