公开(公告)号：US11948829B2

公开(公告)日：2024-04-02

申请号：US17682425

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang

IPC: H01L21/762 ,  H01L21/3065 ,  H10B10/00

CPC classification number: H01L21/76224 ,  H01L21/3065 ,  H01L21/76232 ,  H10B10/12

Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

公开(公告)号：US11937416B2

公开(公告)日：2024-03-19

申请号：US17750649

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US20230387326A1

公开(公告)日：2023-11-30

申请号：US18359280

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L29/78696 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H10B10/125

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

公开(公告)号：US11737255B2

公开(公告)日：2023-08-22

申请号：US17651834

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang

IPC: H10B10/00 ,  H01L23/528 ,  H01L27/092

CPC classification number: H10B10/12 ,  H01L23/5286 ,  H01L27/0924

Abstract: A semiconductor device includes a first memory cell and a dummy region adjacent to the first memory cell. The first memory cell includes a first transistor. The dummy region includes a cut-off transistor. The cut-off transistor has a first terminal electrically coupled to a second terminal of the first transistor. The cut-off transistor has a third terminal electrically coupled to ground.

公开(公告)号：US20230063098A1

公开(公告)日：2023-03-02

申请号：US17462634

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin ,  Yu-Kuan Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

Abstract: A method includes providing a substrate, a source/drain (S/D) feature and semiconductor channel layers over the substrate, a high-k metal gate (HKMG) wrapping around the channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL. The channel layers are spaced one from another along a direction perpendicular to a top surface of the substrate and connect to the S/D feature. The method further includes etching the ILD layer and the CESL to expose a top portion of the S/D feature; etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the channel layers; and forming a metallic contact in the S/D contact trench.

公开(公告)号：US20220375944A1

公开(公告)日：2022-11-24

申请号：US17871764

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  G11C11/412

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US11508738B2

公开(公告)日：2022-11-22

申请号：US17036487

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  G11C11/412

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US20220352181A1

公开(公告)日：2022-11-03

申请号：US17813782

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US20220319583A1

公开(公告)日：2022-10-06

申请号：US17843241

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: G11C11/412 ,  H01L21/475 ,  H01L27/11 ,  G11C11/419

Abstract: Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US20220173113A1

公开(公告)日：2022-06-02

申请号：US17651834

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/528

Abstract: A semiconductor device includes a first memory cell and a dummy region adjacent to the first memory cell. The first memory cell includes a first transistor. The dummy region includes a cut-off transistor. The cut-off transistor has a first terminal electrically coupled to a second terminal of the first transistor. The cut-off transistor has a third terminal electrically coupled to ground.