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公开(公告)号：US11664793B2
公开(公告)日：2023-05-30
申请号：US17571227
申请日：2022-01-07
发明人： Mao-Hsuan Chou , Ya-Tin Chang , Ruey-Bin Sheen , Chih-Hsien Chang
CPC分类号： H03K5/14 , H03K5/135 , H03L7/0891 , H03K2005/00104
摘要： A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.
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公开(公告)号：US11228304B2
公开(公告)日：2022-01-18
申请号：US16952630
申请日：2020-11-19
发明人： Mao-Hsuan Chou , Ya-Tin Chang , Ruey-Bin Sheen , Chih-Hsien Chang
摘要： A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.
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公开(公告)号：US10928447B2
公开(公告)日：2021-02-23
申请号：US16575275
申请日：2019-09-18
发明人： Mao-Hsuan Chou , Ya-Tin Chang , Ruey-Bin Sheen , Chih-Hsien Chang
IPC分类号： G01R31/317 , H03L7/18 , H03L7/085
摘要： An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).
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公开(公告)号：US10749537B2
公开(公告)日：2020-08-18
申请号：US16689719
申请日：2019-11-20
摘要： Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.
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公开(公告)号：US10222412B2
公开(公告)日：2019-03-05
申请号：US15170707
申请日：2016-06-01
发明人： Po-Zeng Kang , Chih-Hsien Chang , Wen-Shen Chou , Yung-Chow Peng
摘要： An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
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公开(公告)号：US20190058575A1
公开(公告)日：2019-02-21
申请号：US16107596
申请日：2018-08-21
发明人： Tsung-Hsien Tsai , Chih-Hsien Chang
CPC分类号： H04L7/0331 , H03L7/091 , H03L7/093 , H03L7/0994 , H03L2207/50
摘要： A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
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公开(公告)号：US10090994B2
公开(公告)日：2018-10-02
申请号：US15845193
申请日：2017-12-18
发明人： Tsung-Hsien Tsai , Chih-Hsien Chang
摘要： A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
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公开(公告)号：US09853807B2
公开(公告)日：2017-12-26
申请号：US15135212
申请日：2016-04-21
发明人： Tsung-Hsien Tsai , Chih-Hsien Chang
CPC分类号： H03L7/093 , H03L7/091 , H03L7/0994 , H03L2207/50
摘要： A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
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