公开(公告)号：US10700264B2

公开(公告)日：2020-06-30

申请号：US16511862

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

公开(公告)号：US20200098978A1

公开(公告)日：2020-03-26

申请号：US16510296

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.

公开(公告)号：US10461246B2

公开(公告)日：2019-10-29

申请号：US15706709

申请日：2017-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  David Dai ,  Chung-Ju Lee

IPC: H01L47/00 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L27/24 ,  H01L43/08

Abstract: A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.

公开(公告)号：US10355198B2

公开(公告)日：2019-07-16

申请号：US15811405

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.

公开(公告)号：US10270028B1

公开(公告)日：2019-04-23

申请号：US15813055

申请日：2017-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Chih-Wei Lu ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22

Abstract: A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.

公开(公告)号：US20180301416A1

公开(公告)日：2018-10-18

申请号：US16017039

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/528 ,  H01L23/538 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.

公开(公告)号：US09633949B2

公开(公告)日：2017-04-25

申请号：US15153967

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.

公开(公告)号：US11329216B2

公开(公告)日：2022-05-10

申请号：US16847447

申请日：2020-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate, a bottom electrode, a magnetic tunneling junction (MTJ), a top electrode, and a residue. The bottom electrode is disposed over the semiconductor substrate. The MTJ is disposed over the bottom electrode. The top electrode is disposed over the MTJ layer. Sidewalls of the bottom electrode, the MTJ, and the top electrode are vertically aligned with each other. The residue of the MTJ is located on the sidewall of the bottom electrode.

公开(公告)号：US11050018B2

公开(公告)日：2021-06-29

申请号：US16664813

申请日：2019-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  David Dai ,  Chung-Ju Lee

IPC: H01L47/00 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L27/24 ,  H01L43/08

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.

公开(公告)号：US11018027B2

公开(公告)日：2021-05-25

申请号：US16988609

申请日：2020-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: An interconnect structure includes a first dielectric layer, an etch stop layer, a conductive via, a conductive line, an intermediate conductive layer, a conductive pillar, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The conductive via is in the first dielectric layer and the etch stop layer. The conductive line is over the conductive via. The intermediate conductive layer is over the conductive line. The conductive pillar is over the intermediate conductive layer. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, and a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.