公开(公告)号：US11856866B2

公开(公告)日：2023-12-26

申请号：US17740145

申请日：2022-05-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC分类号： H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC分类号： H10N50/10 ,  G11C11/161 ,  H01L23/5226 ,  H10B61/00 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

摘要： A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.

公开(公告)号：US11652054B2

公开(公告)日：2023-05-16

申请号：US17236234

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76895

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US11569096B2

公开(公告)日：2023-01-31

申请号：US17327580

申请日：2021-05-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC分类号： H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

摘要： An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

公开(公告)号：US10964888B2

公开(公告)日：2021-03-30

申请号：US16840100

申请日：2020-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Pin-Ren Dai ,  Chung-Ju Lee ,  Chung-Te Lin ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Tai-Yen Peng ,  Chien-Min Lee ,  Wei-Hao Liao

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

公开(公告)号：US11521896B2

公开(公告)日：2022-12-06

申请号：US17012427

申请日：2020-09-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L27/092

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via.

公开(公告)号：US20210391296A1

公开(公告)日：2021-12-16

申请号：US16898670

申请日：2020-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/00 ,  H01L21/768

摘要： The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

公开(公告)号：US20210375751A1

公开(公告)日：2021-12-02

申请号：US16887475

申请日：2020-05-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

摘要： Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.

公开(公告)号：US11171284B2

公开(公告)日：2021-11-09

申请号：US16914296

申请日：2020-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

摘要： A memory device includes a bottom electrode, an MTJ stack, and a top electrode. The bottom electrode has a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall. The MTJ stack is over the bottom electrode. The MTJ stack includes a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer. The bottom magnetic layer has a sidewall coterminous with the upper sidewall of the bottom electrode. The top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode. The top electrode is over the MTJ stack.

公开(公告)号：US20210082698A1

公开(公告)日：2021-03-18

申请号：US16571407

申请日：2019-09-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L21/033 ,  H01L21/768

摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

公开(公告)号：US11854836B2

公开(公告)日：2023-12-26

申请号：US18161701

申请日：2023-01-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC分类号： H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L21/486 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14

摘要： An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.