公开(公告)号：US11631736B2

公开(公告)日：2023-04-18

申请号：US16901631

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522

Abstract: A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.

公开(公告)号：US20230084821A1

公开(公告)日：2023-03-16

申请号：US18055498

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.

公开(公告)号：US11575047B2

公开(公告)日：2023-02-07

申请号：US17318362

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3213

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

公开(公告)号：US11515211B2

公开(公告)日：2022-11-29

申请号：US16887273

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L21/82 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08

Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.

公开(公告)号：US20220344352A1

公开(公告)日：2022-10-27

申请号：US17859757

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

公开(公告)号：US20210384198A1

公开(公告)日：2021-12-09

申请号：US16895678

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

公开(公告)号：US11107735B2

公开(公告)日：2021-08-31

申请号：US16696121

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

公开(公告)号：US20190139836A1

公开(公告)日：2019-05-09

申请号：US15806603

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/0274 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.

公开(公告)号：US10217815B1

公开(公告)日：2019-02-26

申请号：US15796968

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Feng-Cheng Yang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

公开(公告)号：US20240387028A1

公开(公告)日：2024-11-21

申请号：US18785858

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: G16H40/20 ,  G06Q10/20 ,  G06Q50/163 ,  G16H40/63 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H04L9/40

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride and ammonia.