公开(公告)号：US10325964B2

公开(公告)日：2019-06-18

申请号：US15352172

申请日：2016-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Ker-Hsiao Huo ,  Li-Hsuan Yeh ,  Yu-Bin Zhao

IPC: H01L29/08 ,  H01L27/32 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49

Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.

公开(公告)号：US20180138250A1

公开(公告)日：2018-05-17

申请号：US15352172

申请日：2016-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Ker-Hsiao Huo ,  Li-Hsuan Yeh ,  Yu-Bin Zhao

IPC: H01L27/32 ,  H01L29/49 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L51/56 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/3223 ,  H01L27/3225 ,  H01L27/3262 ,  H01L29/41775 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78

Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.

公开(公告)号：US09853149B1

公开(公告)日：2017-12-26

申请号：US15283722

申请日：2016-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Fu-Jier Fan ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ker-Hsiao Huo ,  Szu-Hsien Liu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/7833 ,  Y02E10/50

Abstract: The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.