公开(公告)号：US20210280577A1

公开(公告)日：2021-09-09

申请号：US17316155

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Kong-Beng Thei ,  Fu-Jier Fan ,  Ker-Hsiao Huo ,  Kau-Chu Lin ,  Li-Hsuan Yeh ,  Szu-Hsien Liu ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092

Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.

公开(公告)号：US10164037B2

公开(公告)日：2018-12-25

申请号：US15475294

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker-Hsiao Huo ,  Kong-Beng Thei ,  Chih-Wen Albert Yao ,  Fu-Jier Fan ,  Chen-Liang Chu ,  Ta-Yuan Kung ,  Yi-Huan Chen ,  Yu-Bin Zhao ,  Ming-Ta Lei ,  Li-Hsuan Yeh

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.

公开(公告)号：US10325964B2

公开(公告)日：2019-06-18

申请号：US15352172

申请日：2016-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Ker-Hsiao Huo ,  Li-Hsuan Yeh ,  Yu-Bin Zhao

IPC: H01L29/08 ,  H01L27/32 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49

Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.

公开(公告)号：US20180138250A1

公开(公告)日：2018-05-17

申请号：US15352172

申请日：2016-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Ker-Hsiao Huo ,  Li-Hsuan Yeh ,  Yu-Bin Zhao

IPC: H01L27/32 ,  H01L29/49 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L51/56 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/3223 ,  H01L27/3225 ,  H01L27/3262 ,  H01L29/41775 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78

Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.