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    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    21.
    发明申请
    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200105675A1

    公开(公告)日：2020-04-02

    申请号：US16292348

    申请日：2019-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18 ,  H01L21/56

    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.

    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    23.
    发明申请
    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190355679A1

    公开(公告)日：2019-11-21

    申请号：US15980764

    申请日：2018-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

    IPC: H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56

    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation.

    SEMICONDUCTOR PACKAGE STRUCTURE
    25.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20190096828A1

    公开(公告)日：2019-03-28

    申请号：US15717940

    申请日：2017-09-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Chiang Wu ,  Chun-Lin Lu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Nan-Chin Chuang

    IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01Q21/06 ,  H01Q1/22

    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

    PACKAGE STRUCTURE AND METHOD OF FABRICATING PACKAGE STRUCTURE
    26.
    发明申请
    PACKAGE STRUCTURE AND METHOD OF FABRICATING PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20190067220A1

    公开(公告)日：2019-02-28

    申请号：US15690287

    申请日：2017-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Albert Wan ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang

    IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/48

    Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    28.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220013494A1

    公开(公告)日：2022-01-13

    申请号：US16924192

    申请日：2020-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00

    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    30.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210202354A1

    公开(公告)日：2021-07-01

    申请号：US16897300

    申请日：2020-06-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lipu Kris Chuang ,  Chung-Shi Liu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Ming-Kai Liu ,  Ting-Chu Ko

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L21/48

    Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

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