公开(公告)号：US20200051986A1

公开(公告)日：2020-02-13

申请号：US16654164

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/165 ,  H01L27/092 ,  H01L29/36 ,  H01L29/10 ,  H01L29/167 ,  H01L29/08 ,  H01L27/02

Abstract: An IC is provided. The IC includes a plurality of first cells arranged in a column of a first array, and a plurality of second cells arranged in a column of a second array. P-type fin field-effect transistors of the plurality of first cells share a first semiconductor fin including silicon germanium. P-type FinFETs of two adjacent second cells share a second semiconductor fin including Si. The first array is separated from the second array. A length of the second semiconductor fin is shorter than a length of the first semiconductor fin.

公开(公告)号：US20200051980A1

公开(公告)日：2020-02-13

申请号：US16101573

申请日：2018-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first fin, a first gate electrode, a second fin, a second gate electrode, and a first dielectric capping layer. The first fin extends along a direction. The first gate electrode is across the first fin and has a first notched corner. The second fin extends along the direction. The second gate electrode is across the second fin and has a second notched corner. The first dielectric capping layer has a first portion in between the first notched corner and the second notched corner.

公开(公告)号：US20190311969A1

公开(公告)日：2019-10-10

申请号：US16449915

申请日：2019-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L23/367 ,  H01L29/78 ,  H01L23/48 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes doping a substrate with a dopant to form a first well region of a first core circuit and a second well region of a second core circuit; forming first and second semiconductor fins respectively over the first and second well regions and extending along a direction; forming a first gate stack across the first semiconductor fin and a second gate stack across the second semiconductor fin; forming a first source/drain adjoining the first semiconductor fin and a second source/drain adjoining the second semiconductor fin; and forming a first contact over the first source/drain and having a first width measured along the direction and a second contact over the second source/drain and having a second width measured along the direction, wherein the second width of the second contact is greater than the first width of the first contact.

公开(公告)号：US20190287902A1

公开(公告)日：2019-09-19

申请号：US15921368

申请日：2018-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L23/528 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor fin, first and second source/drains, a gate electrode, and a gate contact. The semiconductor fin is disposed on the substrate. The first and second source/drains is disposed on the semiconductor fin. The gate electrode is across the semiconductor fin and exposes the first and second source/drains. The gate contact is disposed on the gate electrode and has an elliptical profile with a major axis extending along a lengthwise direction of the gate electrode when viewed from above the gate contact.

公开(公告)号：US20190096891A1

公开(公告)日：2019-03-28

申请号：US15718344

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10 ,  H01L29/167 ,  H01L27/092

Abstract: An IC is provided. The IC includes a plurality of P-type fin field-effect transistors (FinFETs). At least one first P-type FinFET includes a silicon germanium (SiGe) channel region. At least one second P-type FinFET includes a Si channel region. Source and drain regions of the plurality of P-type FinFETs include SiGe and a p-type impurity.

公开(公告)号：US20170162232A1

公开(公告)日：2017-06-08

申请号：US15438567

申请日：2017-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

IPC: G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417

Abstract: A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.

公开(公告)号：US20250089319A1

公开(公告)日：2025-03-13

申请号：US18962876

申请日：2024-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H10B10/00

Abstract: An integrated circuit (IC) structure includes first and second semiconductor channel patterns extending over a substrate. From a plan view, the second semiconductor channel pattern has a longitudinal axis aligned with a longitudinal axis of the first semiconductor channel pattern, the first semiconductor channel pattern has a first longitudinal side and a second longitudinal side separated from the first longitudinal side by a first distance, and the second channel pattern has a third longitudinal side and a fourth longitudinal side separated from the third longitudinal side by a second distance less than the first distance.

公开(公告)号：US20250056866A1

公开(公告)日：2025-02-13

申请号：US18447802

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775

Abstract: A semiconductor device includes circuit cells having transistors. Each of the transistors includes nanostructures vertically stacked from each other in a Z-direction, a gate structure wrapping around the nanostructures and extending in a Y-direction, and source/drain features on opposite sides of the gate structure in an X-direction. The semiconductor device further includes silicide features over and in contact with the source/drain features. The silicide features extend lower than bottom surfaces of topmost nanostructures of the nanostructures. The semiconductor device further includes source/drain contacts over and in contact with the silicide features. Each of bottom surfaces of the source/drain contacts has a V-shape in an X-Z cross-sectional view.

公开(公告)号：US20240379458A1

公开(公告)日：2024-11-14

申请号：US18784863

申请日：2024-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L21/8238 ,  H01L21/311 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming first and second semiconductor fins extending upwardly from a substrate; forming a dielectric fin between the first and second semiconductor fins; forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first and second semiconductor fins and the dielectric fin; forming a gate strip extending across upper portions of the first semiconductor fin, the dielectric fin, and the second semiconductor fin; patterning the gate strip to form a first gate structure extending across the first semiconductor fin and a second gate structure extending across the second semiconductor fin while leaving the dielectric fin uncovered; and after patterning the gate strip, depositing a high-k dielectric material over the dielectric fin and in contact with a longitudinal end of the first gate structure and a longitudinal end of the second gate structure.

公开(公告)号：US20230378177A1

公开(公告)日：2023-11-23

申请号：US18362764

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H10B12/00 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/0886 ,  H01L29/0692 ,  H01L29/66545 ,  H01L27/0207 ,  H01L21/823431 ,  H10B12/056 ,  H01L29/7855 ,  H01L29/7856 ,  H10B12/36 ,  H01L27/0924 ,  H01L27/1211

Abstract: An IC structure includes first, second, and third circuits. The first circuit includes a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin. The second circuit includes a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin. The third circuit includes a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin. The first gate dielectric layer has a greater thickness than the second gate dielectric layer. The third semiconductor fin has a smaller width than the second semiconductor fin.