公开(公告)号：US20230335619A1

公开(公告)日：2023-10-19

申请号：US18341151

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Jhon Jhy Liaw ,  Kuo-Hua Pan

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

公开(公告)号：US11545573B2

公开(公告)日：2023-01-03

申请号：US16566037

申请日：2019-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768

Abstract: A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

公开(公告)号：US20220254623A1

公开(公告)日：2022-08-11

申请号：US17728369

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

公开(公告)号：US20220216329A1

公开(公告)日：2022-07-07

申请号：US17700812

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/768

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US11315924B2

公开(公告)日：2022-04-26

申请号：US16917778

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

公开(公告)号：US11302692B2

公开(公告)日：2022-04-12

申请号：US16745107

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20220102509A1

公开(公告)日：2022-03-31

申请号：US17033031

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang ,  Jhon Jhy Liaw

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US11282705B2

公开(公告)日：2022-03-22

申请号：US16916116

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/033 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.

公开(公告)号：US11152488B2

公开(公告)日：2021-10-19

申请号：US16547026

申请日：2019-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/28

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers separated vertically from each other and a dummy pattern layer including dielectric material disposed over and separated vertically from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also comprises a gate structure disposed over a channel region, wherein the gate structure wraps around each of the plurality of semiconductor layers and the dummy pattern layer of the nanostructure.

公开(公告)号：US11133224B2

公开(公告)日：2021-09-28

申请号：US16585677

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Yu-San Chien ,  Ta-Chun Lin ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first fin structure with a first composition and a second fin structure with a second composition, oxidizing the first fin structure to form a first oxide layer and oxidizing the second fin structure to form a second oxide layer, removing the second oxide layer formed on the second fin structure, oxidizing the second fin structure to form a third oxide layer over the second fin structure, and forming a first metal gate electrode layer over the first oxide layer and a second metal gate electrode layer over the third oxide layer.