公开(公告)号：US20170309562A1

公开(公告)日：2017-10-26

申请号：US15135493

申请日：2016-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Li-Chun TIEN ,  Pin-Dai SUE

IPC: H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5222 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US20170061056A1

公开(公告)日：2017-03-02

申请号：US14843805

申请日：2015-09-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Zhong ZHUANG ,  Ting-Wei CHIANG ,  Chung-Te LIN ,  Li-Chun TIEN

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/0924

Abstract: A layout of a cell grid comprises a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged horizontally and evenly spaced with a pitch X, and a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged vertically and evenly spaced with a pitch Y, wherein the pitch Y of the fin-shaped OD regions defines width of the cell grid. The layout of the cell grid further comprises a plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in the fin-shaped OD regions and their gates connected to the POLY lines, wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.

Abstract translation: 电池格栅的布局包括电池网中的多个多晶硅（POLY）线，其中POLY线水平地和间距X间隔布置，并且多个鳍状氧化物扩散（OD）区域在 细胞壁，其中鳍状OD区域以间距Y垂直且均匀地间隔布置，其中鳍状OD区域的间距Y限定单元格栅格的宽度。 单元格栅格的布局还包括单元格栅中的多个PMOS晶体管和NMOS晶体管，其中PMOS晶体管和NMOS晶体管的源极节点和漏极节点形成在鳍状OD区域中，其栅极连接到POLY 线，其中所述多个PMOS晶体管和NMOS晶体管连接在一起以在所述电池网格中形成一个或多个CMOS器件。

公开(公告)号：US20230394217A1

公开(公告)日：2023-12-07

申请号：US17834606

申请日：2022-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fei Fan DUAN ,  Li-Chun TIEN ,  Chih-Liang CHEN

IPC: G06F30/398 ,  H01L21/768 ,  H01L21/027

CPC classification number: G06F30/398 ,  H01L21/0273 ,  H01L21/7687

Abstract: Methods and Apparatuses for making an integrated circuit (IC) are disclosed. In accordance with some embodiments, a method including forming one or more decoupling capacitor (DCAP) cells comprising one or more polysilicon (PO) layers openings formed based on one or more photoresist layer openings formed to solve one or more design rule check (DRC) violations. The one or more DCAP cells also provide decoupling capacitors for the IC.

公开(公告)号：US20230317730A1

公开(公告)日：2023-10-05

申请号：US18331011

申请日：2023-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Chi-Yu LU ,  Ting-Yu CHEN ,  Li-Chun TIEN

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11866 ,  H01L2027/11887 ,  H01L2027/11881 ,  H01L2027/11875 ,  H01L2027/11861 ,  H01L2027/11812

Abstract: A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

公开(公告)号：US20190155984A1

公开(公告)日：2019-05-23

申请号：US15965358

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung CHEN ,  Chung-Te LIN ,  Fong-Yuan CHANG ,  Ho Che YU ,  Li-Chun TIEN

IPC: G06F17/50 ,  H01L27/02

Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.

公开(公告)号：US20180183414A1

公开(公告)日：2018-06-28

申请号：US15841950

申请日：2017-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Pen GUO ,  Chi-Lin LIU ,  Shang-Chih HSIEH ,  Jerry Chang-Jui KAO ,  Li-Chun TIEN ,  Lee-Chung LU

IPC: H03K3/0233 ,  H03K23/58 ,  H01L27/02 ,  H03K3/01 ,  H03K19/094

CPC classification number: H03K3/02332 ,  H01L27/0207 ,  H01L27/0233 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879 ,  H03K3/01 ,  H03K3/356121 ,  H03K3/35625 ,  H03K19/094 ,  H03K23/58

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

公开(公告)号：US20240153942A1

公开(公告)日：2024-05-09

申请号：US18415211

申请日：2024-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Lun CHIEN ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/522

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L23/5226

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

公开(公告)号：US20240014203A1

公开(公告)日：2024-01-11

申请号：US18472985

申请日：2023-09-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Sing LI ,  Guo-Huei WU ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  G06F30/392 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  G06F30/392 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/78696

Abstract: An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.

公开(公告)号：US20230197723A1

公开(公告)日：2023-06-22

申请号：US18168065

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali KESHAVARZI ,  Ta-Pen GUO ,  Shu-Hui SUNG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Ting Yu CHEN ,  Min CAO ,  Yung-Chin HOU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/0649 ,  H01L29/495 ,  H01L2924/0002

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US20230154917A1

公开(公告)日：2023-05-18

申请号：US18156605

申请日：2023-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L27/092

Abstract: A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.