公开(公告)号：US10134861B2

公开(公告)日：2018-11-20

申请号：US14509576

申请日：2014-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wen-Han Fang ,  Chang-Yin Chen ,  Ming-Chia Tai ,  Po-Chi Wu

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance.

公开(公告)号：US09583485B2

公开(公告)日：2017-02-28

申请号：US14737066

申请日：2015-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chai-Wei Chang ,  Che-Cheng Chang ,  Po-Chi Wu ,  Yi-Cheng Chao

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/32136 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

Abstract: A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm.

Abstract translation: 提供FinFET器件结构。 FinFET器件结构包括形成在衬底上的隔离结构和形成在衬底上的翅片结构。 FinFET器件结构包括在鳍结构上形成的第一栅极结构和第二栅极结构，并且第一栅极结构在平行于鳍状结构的方向上具有第一宽度，第二栅极结构在平行方向上具有第二宽度 并且第一宽度小于第二宽度。 第一栅极结构包括具有第一高度的第一功函数层。 第二栅极结构包括具有第二高度的第二功函数层，第一高度与第二高度之间的间隙在约1nm至约6nm的范围内。

公开(公告)号：US12176424B2

公开(公告)日：2024-12-24

申请号：US17671230

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

公开(公告)号：US20240379826A1

公开(公告)日：2024-11-14

申请号：US18782065

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

公开(公告)号：US12136572B2

公开(公告)日：2024-11-05

申请号：US17883286

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chai-Wei Chang ,  Po-Chi Wu ,  Wen-Han Fang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/311

Abstract: A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.

公开(公告)号：US20220328662A1

公开(公告)日：2022-10-13

申请号：US17853104

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Po-Chi Wu ,  Che-Cheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/10

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

公开(公告)号：US11271089B2

公开(公告)日：2022-03-08

申请号：US16667218

申请日：2019-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chai-Wei Chang ,  Che-Cheng Chang ,  Po-Chi Wu ,  Yi-Cheng Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/308

Abstract: Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion.

公开(公告)号：US10483370B2

公开(公告)日：2019-11-19

申请号：US15807860

申请日：2017-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chai-Wei Chang ,  Che-Cheng Chang ,  Po-Chi Wu ,  Yi-Cheng Chao

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/76 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/423

Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over a portion of the gate dielectric layer. The gate structure further includes a gate electrode layer formed over a portion of the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer.

公开(公告)号：US09660084B2

公开(公告)日：2017-05-23

申请号：US14851485

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung-Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L21/02 ,  H01L21/30 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

公开(公告)号：US09418994B1

公开(公告)日：2016-08-16

申请号：US14737099

申请日：2015-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Cheng Chao ,  Chai-Wei Chang ,  Po-Chi Wu ,  Jung-Jui Li

IPC: H01L27/00 ,  H01L29/00 ,  H01L21/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/6681

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate, and the substrate includes a first region and a second region. The FinFET device structure includes an isolation structure formed on the substrate and first fin structures formed on the first region. The FinFET device structure also includes second fin structures formed on the second region, and the number of the first fin structures is greater than the number of the second fin structures. The first fin structures have a first height, the second fin structures have a second height, and a gap between the first height and the second height is in a range from about 0.4 nm to about 4 nm.

Abstract translation: 提供了一种翅片场设备结构及其形成方法。 FinFET器件结构包括衬底，并且衬底包括第一区域和第二区域。 FinFET器件结构包括形成在衬底上的隔离结构和形成在第一区域上的第一鳍结构。 FinFET器件结构还包括形成在第二区域上的第二鳍结构，并且第一鳍结构的数量大于第二鳍结构的数量。 第一翅片结构具有第一高度，第二翅片结构具有第二高度，并且第一高度与第二高度之间的间隙在约0.4nm至约4nm的范围内。