公开(公告)号：US20200312817A1

公开(公告)日：2020-10-01

申请号：US16902539

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/532

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US10727205B2

公开(公告)日：2020-07-28

申请号：US15998455

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.

公开(公告)号：US20200027790A1

公开(公告)日：2020-01-23

申请号：US16584824

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/00 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.

公开(公告)号：US10411020B2

公开(公告)日：2019-09-10

申请号：US15691868

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/265 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092

Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.

公开(公告)号：US20190067299A1

公开(公告)日：2019-02-28

申请号：US15691868

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/768 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L27/1104 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/785

Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.

公开(公告)号：US09653295B1

公开(公告)日：2017-05-16

申请号：US14990604

申请日：2016-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: H01L21/00 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11

CPC classification number: H01L27/1116 ,  H01L21/0337 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/00

Abstract: In a method of manufacturing an SRAM, first dummy patterns are formed over a substrate, on which a first to a third mask layer are formed. Intermediate dummy patterns are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the intermediate dummy patterns. The third mask layer is patterned by using the intermediate dummy patterns, by which the second mask layer is patterned, thereby forming second dummy patterns. Sidewall spacer layers are formed on sidewalls of the second dummy patterns. The second dummy patterns are removed, thereby leaving the sidewall spacer layers as hard mask patterns over the substrate, by which the first mask layer is patterned. The substrate is patterned by using the patterned first mask layer. Each of the plurality of SRAM cells is defined by a cell boundary, within which only two first dummy patterns are included.