公开(公告)号：US20240313119A1

公开(公告)日：2024-09-19

申请号：US18673746

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Hsuan Chen ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Hsin-Wen Su ,  Chia-Wei Chen

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78621 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/167 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/456

Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.

公开(公告)号：US12041760B2

公开(公告)日：2024-07-16

申请号：US17884442

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H10B10/00

CPC classification number: H10B10/12

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US20240234421A1

公开(公告)日：2024-07-11

申请号：US18581241

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Lien-Jung Hung ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L27/092

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

公开(公告)号：US20230389256A1

公开(公告)日：2023-11-30

申请号：US18446593

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00

CPC classification number: H10B10/12

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US11670551B2

公开(公告)日：2023-06-06

申请号：US16926528

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Cheng-Ting Ding ,  Chien-Chih Lin ,  Chien-Chih Lee ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Chih Chieh Yeh ,  Po-Kai Hsiao ,  Tsai-Yu Huang

IPC: H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0607 ,  H01L29/1054

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US11581226B2

公开(公告)日：2023-02-14

申请号：US16938340

申请日：2020-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/11 ,  H01L27/092

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

公开(公告)号：US11563013B2

公开(公告)日：2023-01-24

申请号：US17035371

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

公开(公告)号：US20220416046A1

公开(公告)日：2022-12-29

申请号：US17721778

申请日：2022-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Rong Li ,  Shih-Hao Lin ,  Wen-Chun Keng ,  Chih-Chuan Yang ,  Chih-Hsiang Huang ,  Ping-Wei Wang

IPC: H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming a fin, the fin having an epitaxial portion and a base portion protruding from a substrate. Sidewalls of the base portion are tapered with respect to sidewalls of the epitaxial portion. The method also includes depositing a polymeric material on the sidewalls of the epitaxial portion, performing an etching process to modify a profile of the sidewalls of the base portion, such that the sidewalls of the base portion are laterally recessed with a narrowest width of the base portion located under a top surface of the base portion, removing the polymeric material from the sidewalls of the epitaxial portion, depositing an isolation feature on the sidewalls of the base portion, and forming a gate structure engaging the epitaxial portion.

公开(公告)号：US20220384618A1

公开(公告)日：2022-12-01

申请号：US17877221

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US20220262799A1

公开(公告)日：2022-08-18

申请号：US17739758

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Lien Jung Hung ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.