公开(公告)号：US12300592B2

公开(公告)日：2025-05-13

申请号：US18351809

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

公开(公告)号：US20250079428A1

公开(公告)日：2025-03-06

申请号：US18948727

申请日：2024-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11855059B2

公开(公告)日：2023-12-26

申请号：US17808621

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L21/566 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0401

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US11824007B2

公开(公告)日：2023-11-21

申请号：US17690206

申请日：2022-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4885 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US11682599B2

公开(公告)日：2023-06-20

申请号：US16199535

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

公开(公告)号：US11430776B2

公开(公告)日：2022-08-30

申请号：US16902017

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US20220216192A1

公开(公告)日：2022-07-07

申请号：US17701083

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L25/18 ,  H01L27/01 ,  H01L23/31 ,  H01L25/065 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US20220199541A1

公开(公告)日：2022-06-23

申请号：US17690206

申请日：2022-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US20210391314A1

公开(公告)日：2021-12-16

申请号：US16901682

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L25/18 ,  H01L23/538 ,  H01L27/01 ,  H01L23/31 ,  H01L25/065 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US20210272888A1

公开(公告)日：2021-09-02

申请号：US17320858

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683

Abstract: A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.