公开(公告)号：US20250079428A1

公开(公告)日：2025-03-06

申请号：US18948727

申请日：2024-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11430776B2

公开(公告)日：2022-08-30

申请号：US16902017

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11430739B2

公开(公告)日：2022-08-30

申请号：US16437297

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Meng-Liang Lin ,  Shih-Yung Peng ,  Shih-Ting Hung

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.

公开(公告)号：US20190067144A1

公开(公告)日：2019-02-28

申请号：US15939314

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an encapsulant, a plurality of conductive structures, and a second redistribution structure. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die is disposed over the first surface of the first redistribution structure and is electrically connected to the first redistribution structure. The encapsulant encapsulates the die. The conductive structures are disposed on the first surface of the first redistribution structure and penetrates the encapsulant. The conductive structures surround the die. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant.

公开(公告)号：US11094625B2

公开(公告)日：2021-08-17

申请号：US16406600

申请日：2019-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Techi Wong ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Shih-Ting Hung ,  Shin-Puu Jeng

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.

公开(公告)号：US10347574B2

公开(公告)日：2019-07-09

申请号：US15876227

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/49 ,  H01L23/31 ,  H01L25/04 ,  H01L25/07 ,  H01L25/11 ,  H01L23/498 ,  H01L21/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/373 ,  H01L25/075 ,  H01L23/36 ,  H01L23/367

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US20150364575A1

公开(公告)日：2015-12-17

申请号：US14835958

申请日：2015-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US20210391317A1

公开(公告)日：2021-12-16

申请号：US16902017

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US20200013707A1

公开(公告)日：2020-01-09

申请号：US16504324

申请日：2019-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US09911805B2

公开(公告)日：2018-03-06

申请号：US15349100

申请日：2016-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.