公开(公告)号：US11955527B2

公开(公告)日：2024-04-09

申请号：US17351622

申请日：2021-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US11677010B2

公开(公告)日：2023-06-13

申请号：US17080575

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Chiang ,  Chen-Feng Hsu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Yu-Lin Yang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/0245 ,  H01L21/02172 ,  H01L21/02236 ,  H01L21/31056 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US11600720B2

公开(公告)日：2023-03-07

申请号：US17240482

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Chun-Chieh Lu ,  Ming-Yang Li ,  Tzu-Chiang Chen

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/04 ,  H01L29/66 ,  H01L29/20 ,  H01L29/45

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

公开(公告)号：US20220359737A1

公开(公告)日：2022-11-10

申请号：US17814620

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

公开(公告)号：US11444174B2

公开(公告)日：2022-09-13

申请号：US16562416

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Tai Chang ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Tzu-Chung Wang ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Tzu-Chiang Chen

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/10 ,  H01L29/423 ,  H01L21/308

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

公开(公告)号：US11289384B2

公开(公告)日：2022-03-29

申请号：US17114347

申请日：2020-12-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  I-Sheng Chen ,  Lei-Chun Chou

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

公开(公告)号：US20210399054A1

公开(公告)日：2021-12-23

申请号：US16908896

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

公开(公告)号：US11205706B2

公开(公告)日：2021-12-21

申请号：US16657873

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Tung Ying Lee ,  Shao-Ming Yu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chao-Hsien Huang

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/31 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US20210375989A1

公开(公告)日：2021-12-02

申请号：US16885231

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen ,  Xinyu BAO

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device includes a memory cell, a selector layer and a first work function metal layer. The selector layer is disposed between a first electrode and a second electrode over the memory cell. The first work function metal layer is disposed between the selector layer and the first electrode.

公开(公告)号：US20210366819A1

公开(公告)日：2021-11-25

申请号：US16881005

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Jin Cai ,  Yu-Sheng Chen

IPC: H01L23/50 ,  H01L23/44 ,  H01L21/82

Abstract: Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer.