公开(公告)号：US20230369247A1

公开(公告)日：2023-11-16

申请号：US18357421

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/5381 ,  H01L24/96 ,  H01L21/4853 ,  H01L24/20 ,  H01L21/6835 ,  H01L21/561 ,  H01L21/4857 ,  H01L23/5383 ,  H01L24/19 ,  H01L23/5389 ,  H01L23/5386 ,  H01L23/3128 ,  H01L21/568 ,  H01L21/565 ,  H01L2224/214 ,  H01L2221/68372 ,  H01L2224/95001 ,  H01L2924/3511

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

公开(公告)号：US11764165B2

公开(公告)日：2023-09-19

申请号：US17140734

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2924/3511

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

公开(公告)号：US11715755B2

公开(公告)日：2023-08-01

申请号：US16901912

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01G4/30

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

公开(公告)号：US11495559B2

公开(公告)日：2022-11-08

申请号：US16859914

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad.

公开(公告)号：US20220189942A1

公开(公告)日：2022-06-16

申请号：US17687911

申请日：2022-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L25/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/58 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/12

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US11362066B2

公开(公告)日：2022-06-14

申请号：US16831776

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, a second semiconductor die, an insulating layer, and a first dual-damascene connector electrically connected to the first semiconductor die. The first semiconductor die includes a first bonding surface including a die attaching region and a peripheral region connected to the die attaching region. The second semiconductor die is electrically connected to the first semiconductor die, and a second bonding surface of the second semiconductor die is bonded to the first bonding surface in the die attaching region. The insulating layer disposed on the first bonding surface in the peripheral region extends along sidewalls of the second semiconductor die. The first dual-damascene connector includes a first portion disposed on the insulating layer, and a second portion penetrating through the insulating layer and landing on the first bonding surface in the peripheral region.

公开(公告)号：US20210366773A1

公开(公告)日：2021-11-25

申请号：US17391592

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  B23K26/40

Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.

公开(公告)号：US11183475B2

公开(公告)日：2021-11-23

申请号：US16852565

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/00

Abstract: A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies.

公开(公告)号：US20210335735A1

公开(公告)日：2021-10-28

申请号：US16859914

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad.

公开(公告)号：US10366953B2

公开(公告)日：2019-07-30

申请号：US15684224

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

Abstract: An integrated circuit (IC) package with improved performance and reliability is disclosed. The IC package includes an IC die and a routing structure. The IC die includes a conductive via having a peripheral edge. The routing structure includes a conductive structure coupled to the conductive via. The conductive structure may include a cap region, a routing region, and an intermediate region. The cap region may overlap an area of the conductive via. The routing region may have a first width and the intermediate region may have a second width along the peripheral edge of the conductive via, where the second width may be greater than the first width. The intermediate region may be arranged to connect the cap region to the routing region.