公开(公告)号：US12176349B2

公开(公告)日：2024-12-24

申请号：US18335637

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US20240204104A1

公开(公告)日：2024-06-20

申请号：US18591730

申请日：2024-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L21/76227

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US12002719B2

公开(公告)日：2024-06-04

申请号：US18083757

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

公开(公告)号：US11942549B2

公开(公告)日：2024-03-26

申请号：US18064562

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L21/76227

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US11764221B2

公开(公告)日：2023-09-19

申请号：US17157182

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US11532523B2

公开(公告)日：2022-12-20

申请号：US17197925

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

公开(公告)号：US11527653B2

公开(公告)日：2022-12-13

申请号：US17157330

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US20240387729A1

公开(公告)日：2024-11-21

申请号：US18775341

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US20240274476A1

公开(公告)日：2024-08-15

申请号：US18644657

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

公开(公告)号：US11721699B2

公开(公告)日：2023-08-08

申请号：US17157182

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.