-
公开(公告)号：US20230327020A1
公开(公告)日：2023-10-12
申请号：US18331241
申请日：2023-06-08
IPC分类号： H01L29/78 , H01L27/088 , H01L29/66
CPC分类号： H01L29/78391 , H01L27/0886 , H01L29/66545 , H01L29/66795
摘要： An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
-
公开(公告)号：US11757045B2
公开(公告)日：2023-09-12
申请号：US17571561
申请日：2022-01-10
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78675 , H01L29/66757 , H01L29/78684
摘要： A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
-
公开(公告)号：US11715798B2
公开(公告)日：2023-08-01
申请号：US17674061
申请日：2022-02-17
IPC分类号： H01L29/78 , H01L27/088 , H01L29/66
CPC分类号： H01L29/78391 , H01L27/0886 , H01L29/66545 , H01L29/66795
摘要： An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
-
公开(公告)号：US20220262861A1
公开(公告)日：2022-08-18
申请号：US17737032
申请日：2022-05-05
发明人： Hung-Li Chiang , Jung-Piao Chiu , Tzu-Chiang Chen , Yu-Sheng Chen , Xinyu BAO
摘要： A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.
-
公开(公告)号：US20220131011A1
公开(公告)日：2022-04-28
申请号：US17571561
申请日：2022-01-10
IPC分类号： H01L29/786 , H01L29/66
摘要： A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
-
公开(公告)号：US10854605B2
公开(公告)日：2020-12-01
申请号：US16571465
申请日：2019-09-16
发明人： Hung-Li Chiang , Cheng-Yi Peng , Tsung-Yao Wen , Yee-Chia Yeo , Yen-Ming Chen
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L21/3105 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L29/06 , H01L29/08
摘要： A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
-
公开(公告)号：US10756089B2
公开(公告)日：2020-08-25
申请号：US15981167
申请日：2018-05-16
发明人： Hung-Li Chiang , I-Sheng Chen , Tzu-Chiang Chen
IPC分类号： H01L29/06 , H01L27/092 , H01L29/78 , H01L29/786 , H01L21/02 , H01L21/8238 , H01L29/66 , H01L21/324 , H01L29/161
摘要： Present disclosure provides a hybrid semiconductor transistor structure, including a substrate, a first transistor on the substrate, a channel of the first transistor including a fin and having a first channel height, a second transistor adjacent to the first transistor, a channel of the second transistor including a nanowire, and a separation laterally spacing the fin from the nanowire. The first channel height is greater than the separation. Present disclosure also provides a method for manufacturing the hybrid semiconductor transistor structure.
-
公开(公告)号：US20200013779A1
公开(公告)日：2020-01-09
申请号：US16571465
申请日：2019-09-16
发明人： Hung-Li Chiang , Cheng-Yi Peng , Tsung-Yao Wen , Yee-Chia Yeo , Yen-Ming Chen
IPC分类号： H01L27/092 , H01L29/08 , H01L29/06 , H01L21/8238 , H01L21/8234 , H01L21/762 , H01L21/3105 , H01L29/78 , H01L29/66
摘要： A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
-
公开(公告)号：US10153280B2
公开(公告)日：2018-12-11
申请号：US15415641
申请日：2017-01-25
发明人： Hung-Li Chiang , Cheng-Yi Peng , Tsung-Yao Wen , Yee-Chia Yeo , Yen-Ming Chen
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L21/3105 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L29/06 , H01L29/08
摘要： A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
-
公开(公告)号：US09972545B2
公开(公告)日：2018-05-15
申请号：US15485846
申请日：2017-04-12
发明人： Hung-Li Chiang , Chih Chieh Yeh , Cheng-Yi Peng , Tzu-Chiang Chen , Yee-Chia Yeo
IPC分类号： H01L21/8238 , H01L21/3065 , H01L21/265 , H01L21/285 , H01L21/324 , H01L27/092 , H01L29/423 , H01L29/06 , H01L23/535 , H01L29/66
CPC分类号： H01L21/823885 , H01L21/26513 , H01L21/28518 , H01L21/3065 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L23/535 , H01L27/092 , H01L29/0649 , H01L29/42392 , H01L29/66484 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.
-
-
-
-
-
-
-
-
-
搜索结果
104 条记录 (耗时 0.024 秒)
