公开(公告)号：US06333662B1

公开(公告)日：2001-12-25

申请号：US09468924

申请日：1999-12-22

申请人： Akira Umezawa ,  Shigeru Atsumi

发明人： Akira Umezawa ,  Shigeru Atsumi

IPC分类号： H03L500

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/12

摘要： A latch type level shift circuit includes an internal power supply potential generating circuit for generating first and second internal power supply potentials; a latch circuit having first and second nodes and driven by the first and second internal power supply potentials; a level shifter having first and second output terminals and driven by the first internal power supply potential and a fixed potential; a first MOS transistor having a gate applied with the fixed potential; and a second MOS transistor having a gate applied with the fixed potential. The first MOS transistor is connected between the first node and the first output terminal, and the second MOS transistor is connected between the second node and the second output terminal. The internal power supply potential generating circuit may be used to change the values of the first and second internal power supply potentials by setting the first internal power supply potential to the fixed potential and by setting the second internal power supply potential to a negative potential at the time of an erase operation.

摘要翻译： 闩锁型电平移位电路包括用于产生第一和第二内部电源电位的内部电源电位产生电路; 具有第一和第二节点并由第一和第二内部电源电位驱动的锁存电路; 具有第一和第二输出端并由第一内部电源电位和固定电位驱动的电平移位器; 具有施加了固定电位的栅极的第一MOS晶体管; 以及具有施加了固定电位的栅极的第二MOS晶体管。 第一MOS晶体管连接在第一节点和第一输出端子之间，第二MOS晶体管连接在第二节点和第二输出端子之间。 内部电源电位产生电路可以用于通过将第一内部电源电位设定为固定电位并且将第二内部电源电位设置为负电位来改变第一和第二内部电源电位的值 擦除操作的时间。

公开(公告)号：US06256227B1

公开(公告)日：2001-07-03

申请号：US09383188

申请日：1999-08-26

申请人： Shigeru Atsumi ,  Akira Umezawa ,  Toru Tanzawa ,  Seiji Yamada

发明人： Shigeru Atsumi ,  Akira Umezawa ,  Toru Tanzawa ,  Seiji Yamada

IPC分类号： G11C1604

CPC分类号： G11C16/08

摘要： A pattern constituted of a main bit line and four sub-bit lines is repeated around a column sub-selector of the flash EEPROM employing a double bit architecture having four block selection transistors per pitch of the pattern. In the flash EEPROM having a memory cell array and a column selector divided into a plurality of cell blocks 11i and a plurality of column sub selectors 12i, respectively, the column sub-selector including repeated patterns each having four sub bit lines (SBLs) and a single main bit line (MBL) arranged in a column direction. In a pitch of the repeating pattern, active regions for four block selection transistors (BSTs) are arranged. Gate wiring layers of each of the block selection transistors are arranged above the active region in a row direction and four block decode lines (BDLi) are arranged above the active region in the row direction.

摘要翻译： 使用采用具有四个块选择晶体管的双位架构在闪存EEPROM的列子选择器周围重复由主位线和四个子位线构成的图案，每个间距的图案具有四个块选择晶体管。 在具有存储单元阵列的快闪EEPROM和分别分成多个单元块11i和多个列子选择器12i的列选择器中，列子选择器包括各自具有四个子位线（SBL）和 沿列方向布置的单个主位线（MBL）。 在重复图案的间距中，布置了四个块选择晶体管（BST）的有源区。 每个块选择晶体管的栅极布线层被布置在行方向上的有源区上方，并且在行方向上的有源区上方布置四个块解码线（BDLi）。

公开(公告)号：US6111456A

公开(公告)日：2000-08-29

申请号：US030722

申请日：1998-02-25

申请人： Hidetoshi Saito ,  Shigeru Atsumi ,  Akira Umezawa

发明人： Hidetoshi Saito ,  Shigeru Atsumi ,  Akira Umezawa

IPC分类号： H03K3/356 ,  G01K7/00 ,  H03K19/0948 ,  G05F1/10

CPC分类号： G01K7/00

摘要： A semiconductor circuit comprises an I-type of NMOS transistors N15 and N16 connected between a power supply voltage VDD and a ground electrode. The gate electrode of the NMOS transistor N15 is set to a reference voltage VREF that is lower than the power supply voltage VDD. The drain voltage VD of the NMOS transistor N16 is almost equal to the reference voltage VREF, and the NMOS transistor N16 acts in a linear region. Accordingly, the NMOS transistor N16 acts in the same manner as the resistor element and has no influence on change of the concentration of the diffusion resistor or the power supply voltage VDD.

摘要翻译： 半导体电路包括连接在电源电压VDD和接地电极之间的I型NMOS晶体管N15和N16。 NMOS晶体管N15的栅电极设定为低于电源电压VDD的基准电压VREF。 NMOS晶体管N16的漏极电压VD几乎等于参考电压VREF，并且NMOS晶体管N16作用在线性区域中。 因此，NMOS晶体管N16以与电阻元件相同的方式起作用，并且不影响扩散电阻器的浓度或电源电压VDD的变化。

公开(公告)号：US20100008143A1

公开(公告)日：2010-01-14

申请号：US12475799

申请日：2009-06-01

申请人： Akira Umezawa

发明人： Akira Umezawa

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792

摘要： A nonvolatile semiconductor memory device includes a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of a plurality of trench portions respectively formed in portions between the plurality of active areas formed in a first direction, a plurality of gate electrodes filled in internal portions of the plurality of trench portions with the multi-layer insulating film, a plurality of first metal interconnections formed in a second direction and each functioning as a bit line or source line, and a plurality of first conductivity-type diffusion layer regions arranged in a staggered form in corresponding portions of the plurality of active areas which intersect with the plurality of first metal interconnections. The device further includes a plurality of connection contacts form to respectively connect the plurality of first conductivity-type diffusion layer regions to the plurality of first metal interconnections.

摘要翻译： 非易失性半导体存储器件包括至少具有电荷存储层并且形成在分别形成在沿第一方向形成的多个有源区域之间的部分中的多个沟槽部分的底表面和两个侧表面上的多层绝缘膜， 多个栅电极，多个沟槽部的内部被多层绝缘膜填充，多个第一金属互连形成在第二方向上，并且各自作为位线或源极线，以及多个第一导电性 型扩散层区域以交错的形式布置在与多个第一金属互连相交的多个有效区域的对应部分中。 该装置还包括多个连接触头形式，以将多个第一导电类型扩散层区域分别连接到多个第一金属互连。

公开(公告)号：US07577032B2

公开(公告)日：2009-08-18

申请号：US11924133

申请日：2007-10-25

申请人： Akira Umezawa

发明人： Akira Umezawa

IPC分类号： G11C11/03

CPC分类号： G11C16/08 ,  G11C8/08

摘要： The local row decoder includes a first MOS transistor of a first conductivity type having one end connected to the local word line, the other end supplied with a first voltage, and a gate connected to the global word line, and a second MOS transistor of a second conductivity type having one end connected to the local word line, the other end supplied with a second voltage, and a gate connected to the global word line. The global row decoder is capable of independently selecting either a first global word line or a second global word line. The first global word line is connected to the first MOS transistor and the second MOS transistor both connected to any one of the local word lines. The second global word line is connected to the first MOS transistor and the second MOS transistor both connected to another adjacent local word line.

摘要翻译： 本地排解码器包括第一导电类型的第一MOS晶体管，其一端连接到本地字线，另一端被提供有第一电压，并且连接到全局字线的栅极和第二MOS晶体管， 第二导电类型，其一端连接到本地字线，另一端提供第二电压，以及连接到全局字线的栅极。 全局行解码器能够独立地选择第一全局字线或第二全局字线。 第一全局字线连接到第一MOS晶体管，第二MOS晶体管连接到任何一个本地字线。 第二全局字线连接到第一MOS晶体管，第二MOS晶体管连接到另一相邻的本地字线。

公开(公告)号：US07505355B2

公开(公告)日：2009-03-17

申请号：US11733796

申请日：2007-04-11

申请人： Kazushige Kanda ,  Akira Umezawa ,  Kazuhiko Kakizoe ,  Yoshiaki Hashiba ,  Yoshiharu Hirata

发明人： Kazushige Kanda ,  Akira Umezawa ,  Kazuhiko Kakizoe ,  Yoshiaki Hashiba ,  Yoshiharu Hirata

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115

摘要： A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m

摘要翻译： 半导体存储器件包括存储单元阵列，字线和行解码器。 存储单元阵列包括排列成矩阵的存储单元。 存储单元包括具有电荷累积层的第一MOS晶体管和控制栅极和第二MOS晶体管。 字线连接第一MOS晶体管的控制栅极。 行解码器包括第一地址解码电路，第二地址解码电路和传输门。 第一地址解码电路解码n位行地址信号中的m位（m和n是满足表达式m

公开(公告)号：US20070230246A1

公开(公告)日：2007-10-04

申请号：US11690420

申请日：2007-03-23

申请人： Akira Umezawa ,  Jin Kashiwagi

发明人： Akira Umezawa ,  Jin Kashiwagi

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C29/00

CPC分类号： G11C16/26 ,  G11C16/04 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24

摘要： A non-volatile semiconductor memory device comprises a redundant memory cell to store address data of a defect cell in a memory cell array. A first decoder circuit is given a first drive voltage to provide a control signal to the redundant memory cell. A dummy memory cell has a threshold voltage corresponding to the redundant memory cell. A second decoder circuit is given a second drive voltage corresponding to the first drive voltage to provide a control signal to the dummy memory cell. A comparator circuit compares data to be read out of the dummy memory cell with data actually read out of the dummy memory cell.

摘要翻译： 非易失性半导体存储器件包括用于存储存储单元阵列中的缺陷单元的地址数据的冗余存储单元。 第一解码器电路被给予第一驱动电压以向冗余存储器单元提供控制信号。 虚拟存储单元具有对应于冗余存储单元的阈值电压。 第二解码器电路被给予对应于第一驱动电压的第二驱动电压，以向虚拟存储器单元提供控制信号。 比较器电路将要从虚拟存储器单元读出的数据与从虚拟存储单元实际读出的数据进行比较。

公开(公告)号：US20070109876A1

公开(公告)日：2007-05-17

申请号：US11471681

申请日：2006-06-21

申请人： Akira Umezawa

发明人： Akira Umezawa

IPC分类号： G11C5/14

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C5/147 ,  G11C16/0433

摘要： A semiconductor memory device includes memory cells, a memory cell array, a first voltage generating circuit, a reference voltage generating circuit, and a first voltage control circuit. Each of the memory cells includes a first MOS transistor comprising a floating gate and a control gate formed on the floating gate. The memory cell array includes the memory cells arranged in a matrix. The first voltage generating circuit generates a first positive voltage. The reference voltage generating circuit generates a first reference voltage. The first voltage control circuit sets the first positive voltage at a voltage value based on the first reference voltage and outputs a resulting second positive voltage. An output impedance of the first voltage control circuit varies depending on the number of bits into which data is simultaneously written. The second positive voltage is used to write and erase data into and from the memory cells.

摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，第一电压产生电路，参考电压产生电路和第一电压控制电路。 每个存储单元包括第一MOS晶体管，其包括形成在浮置栅极上的浮置栅极和控制栅极。 存储单元阵列包括排列成矩阵的存储单元。 第一电压产生电路产生第一正电压。 参考电压产生电路产生第一参考电压。 第一电压控制电路基于第一参考电压将第一正电压设置在电压值，并输出所得到的第二正电压。 第一电压控制电路的输出阻抗根据同时写入数据的位数而变化。 第二个正电压用于将数据写入和擦除存储单元。

公开(公告)号：US07120057B2

公开(公告)日：2006-10-10

申请号：US11016804

申请日：2004-12-21

申请人： Akira Umezawa ,  Kazuhiko Kakizoe

发明人： Akira Umezawa ,  Kazuhiko Kakizoe

IPC分类号： G11C16/04

CPC分类号： H01L27/105 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/11531

摘要： A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.

公开(公告)号：US20060083072A1

公开(公告)日：2006-04-20

申请号：US11248425

申请日：2005-10-13

申请人： Akira Umezawa

发明人： Akira Umezawa

IPC分类号： G11C16/04

CPC分类号： H01L27/11526 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546

摘要： A semiconductor memory device comprises a memory cell array, word lines, select gate lines, and switch elements. The memory cell array includes a plurality of memory cells arranged in a matrix. Each of the memory cells includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor which has a drain connected to a source of the first MOS transistor. Each of the word lines connects commonly the control gates of the first MOS transistors in a same row. Each of the select gate lines connects commonly the gates of the second MOS transistors in a same row. The switch elements, in an erase operation, electrically connect the select gate lines to a semiconductor substrate in which the memory cell array is formed.

摘要翻译： 半导体存储器件包括存储单元阵列，字线，选择栅线和开关元件。 存储单元阵列包括以矩阵形式布置的多个存储单元。 每个存储单元包括具有电荷累积层和控制栅极的第一MOS晶体管和具有连接到第一MOS晶体管的源极的漏极的第二MOS晶体管。 每个字线通常连接在同一行中的第一MOS晶体管的控制栅极。 每个选择栅极线共同连接在同一行中的第二MOS晶体管的栅极。 在擦除操作中的开关元件将选择栅极线电连接到其中形成存储单元阵列的半导体衬底。