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公开(公告)号：US07345334B2
公开(公告)日：2008-03-18
申请号：US10908081
申请日：2005-04-27
IPC分类号： H01L29/72
CPC分类号： H01L27/1203 , H01L27/0805 , H01L29/94
摘要： A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer or a thickened portion of a surface silicon layer. The other capacitor plate may be doped polysilicon and separated from the first capacitor plate by capacitor dielectric, e.g., CVD or thermal oxide. Contacts to each of the capacitor plates directly connect and extend from the respective plates, such that direct contact is available from both plates.
摘要翻译： 可以是分立电容器的半导体结构，包括具有离散这种电容器的电路和/或由这种分立电容器去耦合的片上绝缘体（SOI）集成电路（IC）和片上去耦电容器（decap））。 一个电容器板可以是硅本体层中的阱（N阱或P阱）或表面硅层的增厚部分。 另一个电容器板可以是掺杂多晶硅并且通过电容器电介质例如CVD或热氧化物与第一电容器板分离。 与每个电容器板的接触件从相应的板直接连接和延伸，使得从两个板可以直接接触。
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公开(公告)号：US07115968B2
公开(公告)日：2006-10-03
申请号：US10971238
申请日：2004-10-22
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。
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公开(公告)号：US06472230B2
公开(公告)日：2002-10-29
申请号：US10102381
申请日：2002-03-20
IPC分类号： H01L2100
CPC分类号： H01L23/5258 , G11C11/5607 , G11C2216/26 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable.
摘要翻译： 一种用于可编程电路的方法和结构，其包括具有可改变的磁阻的磁性装置。
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公开(公告)号：US06271059B1
公开(公告)日：2001-08-07
申请号：US09225148
申请日：1999-01-04
IPC分类号： H01L2144
CPC分类号： H01L23/13 , H01L24/05 , H01L24/81 , H01L2224/0401 , H01L2224/81136 , H01L2224/81141 , H01L2224/81192 , H01L2224/81365 , H01L2224/81801 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/19041
摘要： A method for fabricating a connector structure for interconnecting integrated circuit chips. The method includes the steps of patterning, masking and etching a substrate to form protrusions on the top and/or bottom surfaces of the substrate. Then the protrusions are preferentially etched to form truncated protrusions. An integrated circuit chip having pads on its surface is then joined to the top and/or bottom sides of the substrate. The protrusions and pads are coated with an electrically conductive metal. The substrate and the integrated circuit chips are joined and aligned together such that the truncated protrusions mate with the pads. Metal-coated vias are formed through the substrate to electrically connect the integrated circuit chips on the surfaces of the substrate.
摘要翻译： 一种用于制造用于互连集成电路芯片的连接器结构的方法。 该方法包括对衬底进行图案化，掩模和蚀刻以在衬底的顶表面和/或底表面上形成凸起的步骤。 然后优先蚀刻突起以形成截短的突起。 然后，在其表面上具有焊盘的集成电路芯片接合到衬底的顶部和/或底部。 突起和垫被涂覆有导电金属。 基板和集成电路芯片被接合并对齐在一起，使得截短的突起与焊盘配合。 通过衬底形成金属涂覆的通孔，以电连接衬底表面上的集成电路芯片。
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公开(公告)号：US06256184B1
公开(公告)日：2001-07-03
申请号：US09334088
申请日：1999-06-16
IPC分类号： H02H322
CPC分类号： H01L27/0251 , H01L27/0266
摘要： An ESD protection method and apparatus are provided for an IC chip having an I/O pad and I/O circuitry coupled to the I/O pad. A low threshold voltage FET is coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad. The FET also is coupled to a first voltage terminal of the I/O circuitry for providing a shunting path for the ESD event, thereby effectuating the protecting of the IC chip from the ESD event on the I/O pad. A first control circuit is coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET, thereby maintaining the FET in an off state during normal operation of the IC chip. Preferably a second control circuit is coupled between the FET and the first voltage terminal and operates in conjunction with the first control circuit for maintaining the FET in an off state during normal operation of the IC chip. The first control circuit preferably comprises a short circuit between the gate of the FET and the first voltage terminal, an inverter coupled between the gate of the FET and a second voltage terminal or a negative bias generator coupled to the gate of the FET. The second control circuit preferably comprises a short circuit between the FET and the first voltage terminal or a diode coupled between the FET and the first voltage terminal.
摘要翻译： 为具有耦合到I / O焊盘的I / O焊盘和I / O电路的IC芯片提供ESD保护方法和装置。 低阈值电压FET与I / O电路并联耦合到I / O焊盘，以保护IC芯片免受I / O焊盘上的ESD事件。 FET还耦合到I / O电路的第一电压端子，用于为ESD事件提供分流路径，从而实现IC芯片免受I / O焊盘上的ESD事件的保护。 第一控制电路耦合到FET的栅极，用于将栅极保持在低于FET阈值电压的电压电平，从而在IC芯片正常工作期间保持FET处于截止状态。 优选地，第二控制电路耦合在FET和第一电压端子之间，并且与第一控制电路一起操作，以在IC芯片的正常操作期间将FET保持在截止状态。 第一控制电路优选地包括在FET的栅极和第一电压端子之间的短路，耦合在FET的栅极和耦合到FET的栅极的第二电压端子或负偏压发生器之间的反相器。 第二控制电路优选地包括FET和第一电压端子之间的短路或耦合在FET和第一电压端子之间的二极管。
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公开(公告)号：US08745571B2
公开(公告)日：2014-06-03
申请号：US13026451
申请日：2011-02-14
申请人： Hongmei Li , Richard Q. Williams
发明人： Hongmei Li , Richard Q. Williams
IPC分类号： G06F15/04
CPC分类号： G06F17/5018 , G06F17/5068
摘要： The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.
摘要翻译： 本公开涉及补偿布局形状的分析。 根据实施例的方法包括：使用铲斗结构分析半导体布局，所述布局包括半导体器件; 以及将图案模板应用到所述桶结构的内容以识别与所述半导体器件相邻的形状; 其中，图案模板是从布局基本原理中导出的。
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27.发明授权Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure 有权绝缘体上半导体（SOI）结构，具有选择性放置的亚绝缘体层空穴和形成SOI结构的方法公开(公告)号：US08610211B2
公开(公告)日：2013-12-17
申请号：US12842146
申请日：2010-07-23
IPC分类号： H01L27/12
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译： 公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二 半导体层和衬底的截面。 第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。 或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。 例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合 这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。 此外，公开了形成这种SOI结构的相关方法。
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公开(公告)号：US20110115054A1
公开(公告)日：2011-05-19
申请号：US12621956
申请日：2009-11-19
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
IPC分类号： H01L29/73 , H01L29/06 , H01L21/331
CPC分类号： H01L31/03529 , H01L27/14643 , H01L29/0657 , H01L29/6609 , H01L29/66136 , H01L29/66234 , H01L29/732 , H01L29/8611 , H01L29/868 , H01L31/0352 , H01L31/103 , Y02E10/50
摘要： A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.
摘要翻译： 二极管包括由具有第一掺杂极性的第一材料形成的衬底。 衬底具有平坦表面和从平面表面延伸的至少一个半球形结构。 半球形结构由第一材料形成。 第二材料层在半球形结构之上。 第二材料包括与第一掺杂极性相反的第二掺杂极性。 第二材料层符合半球形结构的形状。 第一电触头连接到基板，第二电触点连接到第二材料层。 通过在原始层上制造附加层来形成附加的半导体结构。
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公开(公告)号：US07786549B2
公开(公告)日：2010-08-31
申请号：US11527343
申请日：2006-09-26
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。
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公开(公告)号：US07732865B2
公开(公告)日：2010-06-08
申请号：US11684306
申请日：2007-03-09
IPC分类号： H01L29/72
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/84 , H01L27/1203
摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.
摘要翻译： 本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。 利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。
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