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    Epitaxial imprinting
    1.
    发明授权
    Epitaxial imprinting 失效
    外延印记

    公开(公告)号：US07732865B2

    公开(公告)日：2010-06-08

    申请号：US11684306

    申请日：2007-03-09

    申请人： Toshiharu Furukawa ,  Carl Radens ,  William R. Tonti ,  Richard Q. Williams

    发明人： Toshiharu Furukawa ,  Carl Radens ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L29/72

    CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/1203

    摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

    摘要翻译： 本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。 利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

    Structure and method for thin box SOI device
    3.
    发明授权
    Structure and method for thin box SOI device 有权
    薄盒SOI器件的结构和方法

    公开(公告)号：US07217604B2

    公开(公告)日：2007-05-15

    申请号：US10906014

    申请日：2005-01-31

    申请人： Toshiharu Furukawa ,  Carl J. Radens ,  William R. Tonti ,  Richard Q. Williams

    发明人： Toshiharu Furukawa ,  Carl J. Radens ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66772 ,  H01L29/665 ,  H01L29/78606 ,  H01L29/78612

    摘要： A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.

    摘要翻译： 一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物， 在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻， 在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在 器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

    Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application
    6.
    发明授权
    Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application 失效
    硅抗熔丝结构，绝缘体上的体和硅绝缘体制造方法和应用

    公开(公告)号：US06396120B1

    公开(公告)日：2002-05-28

    申请号：US09527191

    申请日：2000-03-17

    申请人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

    发明人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L2972

    CPC分类号： H01L29/78696 ,  H01L21/823412 ,  H01L21/823456 ,  H01L23/5252 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.

    摘要翻译： 一种使用场强增强区域的方法和半导体结构，其中氧化物厚度大大降低，从而允许在不损坏标准CMOS逻辑的老化电压下进行反熔丝编程。 半导体器件包括具有突出的突起终止于基本尖锐点的衬底，凸起突起上的绝缘体层足够薄以致被施加到尖锐点的击穿电压所破坏，由绝缘体上的材料构成的区域 在绝缘体层被击穿电压破坏之后用于电耦合到衬底的凸起突起，以及用于向衬底提供击穿电压的触点。 在第二实施例中，半导体器件包括在衬底的顶表面中形成有槽的衬底，在衬底的顶表面上方的相对较厚的绝缘体层，在槽的相对较薄的绝缘体层，其被破坏 电压施加到槽，由比较薄的绝缘体层上的材料组成的区域，该沟槽在相对较薄的绝缘体层被击穿电压破坏之后用于变成与电极耦合的衬底;以及用于将击穿电压提供给 所述基板。

    Method of closing an antifuse using laser energy
    7.
    发明授权
    Method of closing an antifuse using laser energy 失效
    使用激光能量封闭反熔丝的方法

    公开(公告)号：US07115968B2

    公开(公告)日：2006-10-03

    申请号：US10971238

    申请日：2004-10-22

    申请人： William T. Motsiff ,  William R. Tonti ,  Richard Q. Williams

    发明人： William T. Motsiff ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5252 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

    摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。

    Chip interconnection structure using stub terminals
    8.
    发明授权
    Chip interconnection structure using stub terminals 有权
    使用短截线端子的芯片互连结构

    公开(公告)号：US06271059B1

    公开(公告)日：2001-08-07

    申请号：US09225148

    申请日：1999-01-04

    申请人： Claude L. Bertin ,  William R. Tonti ,  Richard Q. Williams

    发明人： Claude L. Bertin ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L2144

    CPC分类号： H01L23/13 ,  H01L24/05 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81192 ,  H01L2224/81365 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041

    摘要： A method for fabricating a connector structure for interconnecting integrated circuit chips. The method includes the steps of patterning, masking and etching a substrate to form protrusions on the top and/or bottom surfaces of the substrate. Then the protrusions are preferentially etched to form truncated protrusions. An integrated circuit chip having pads on its surface is then joined to the top and/or bottom sides of the substrate. The protrusions and pads are coated with an electrically conductive metal. The substrate and the integrated circuit chips are joined and aligned together such that the truncated protrusions mate with the pads. Metal-coated vias are formed through the substrate to electrically connect the integrated circuit chips on the surfaces of the substrate.

    摘要翻译： 一种用于制造用于互连集成电路芯片的连接器结构的方法。 该方法包括对衬底进行图案化，掩模和蚀刻以在衬底的顶表面和/或底表面上形成凸起的步骤。 然后优先蚀刻突起以形成截短的突起。 然后，在其表面上具有焊盘的集成电路芯片接合到衬底的顶部和/或底部。 突起和垫被涂覆有导电金属。 基板和集成电路芯片被接合并对齐在一起，使得截短的突起与焊盘配合。 通过衬底形成金属涂覆的通孔，以电连接衬底表面上的集成电路芯片。

    Doped single crystal silicon silicided eFuse
    9.
    发明授权
    Doped single crystal silicon silicided eFuse 有权
    掺杂单晶硅硅片eFuse

    公开(公告)号：US07572724B2

    公开(公告)日：2009-08-11

    申请号：US12043226

    申请日：2008-03-06

    申请人： Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti ,  Richard Q. Williams

    发明人： Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L21/00

    CPC分类号： H01L27/10 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.

    摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。 将单晶硅层图案化成条带。 在构图之前或之后，单晶硅层掺杂有一种或多种杂质。 至少单晶硅层的上部然后被硅化以形成硅化带。 在一个实施例中，整个单晶硅带被硅化以产生硅化物条。 在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。 在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。 通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。 上覆的硅化物材料允许熔丝作为未编程状态的导体。 然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。