公开(公告)号：US11879940B2

公开(公告)日：2024-01-23

申请号：US17355386

申请日：2021-06-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan

IPC: G01R31/3177 ,  G01R31/317 ,  G11C29/56 ,  G06F11/10 ,  G11C29/36 ,  G11C29/42

CPC classification number: G01R31/3177 ,  G01R31/31718 ,  G01R31/31724 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/36 ,  G11C29/42 ,  G11C29/56004 ,  G11C2029/3602 ,  G11C2029/5602

Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.

公开(公告)号：US11333707B2

公开(公告)日：2022-05-17

申请号：US16703909

申请日：2019-12-05

Applicant: Texas Instruments Incorporated

Inventor： Khushboo Agarwal ,  Sanjay Krishna Hulical Vijayaraghavachar ,  Raashid Moin Shaikh ,  Srivaths Ravi ,  Wilson Pradeep ,  Rajesh Kumar Tiwari

IPC: G06F30/33 ,  G01R31/317

Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

公开(公告)号：US10776546B2

公开(公告)日：2020-09-15

申请号：US16410391

申请日：2019-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan ,  Saket Jalan

IPC: G06F17/50 ,  G01R27/28 ,  G01R31/28 ,  G01R31/36 ,  G06G7/62 ,  G06F30/3312 ,  G06F30/30 ,  G06F30/398 ,  H01L23/58 ,  H01L25/00 ,  H01L29/10 ,  H03K19/00 ,  G06F30/392 ,  G06F30/394

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

公开(公告)号：US10184980B2

公开(公告)日：2019-01-22

申请号：US15395307

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naman Maheshwari ,  Wilson Pradeep ,  Prakash Narayanan

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3193

Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.

公开(公告)号：US20180128877A1

公开(公告)日：2018-05-10

申请号：US15347619

申请日：2016-11-09

Applicant: Texas Instruments Incorporated

Inventor： Wilson Pradeep

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31707 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/318385 ,  G01R31/318547

Abstract: Described examples include a method of providing K bits of test data to a combinatorial circuit. The method further includes generating N bits of test data using the combinatorial circuit, where N is greater than K. The method further includes providing the N bits of test data to a module under test.