公开(公告)号：US20080044957A1

公开(公告)日：2008-02-21

申请号：US11870631

申请日：2007-10-11

Applicant: James Chambers ,  Mark Visokay ,  Luigi Colombo ,  Antonio Rotondaro

Inventor： James Chambers ,  Mark Visokay ,  Luigi Colombo ,  Antonio Rotondaro

IPC: H01L21/84

CPC classification number: H01L21/823842

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract translation: 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

公开(公告)号：US20070122962A1

公开(公告)日：2007-05-31

申请号：US11620447

申请日：2007-01-05

Applicant: James Chambers ,  Mark Visokay ,  Luigi Colombo

Inventor： James Chambers ,  Mark Visokay ,  Luigi Colombo

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

Abstract translation: 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

公开(公告)号：US20070037343A1

公开(公告)日：2007-02-15

申请号：US11200741

申请日：2005-08-10

Applicant: Luigi Colombo ,  James Chambers ,  Mark Visokay

Inventor： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

公开(公告)号：US20060043524A1

公开(公告)日：2006-03-02

申请号：US11221103

申请日：2005-09-07

Applicant: Mark Visokay ,  James Chambers

Inventor： Mark Visokay ,  James Chambers

IPC: H01L29/00

CPC classification number: H01L29/7831 ,  H01L29/66484

Abstract: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

公开(公告)号：US20050124121A1

公开(公告)日：2005-06-09

申请号：US10731647

申请日：2003-12-09

Applicant: Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

Inventor： Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

IPC: C23C16/56 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8242 ,  H01L29/51

CPC classification number: H01L21/02318 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: The present invention pertains to annealing a high dielectric constant (high-k) material in a manner that substantially reduces or eliminates disadvantages and problems heretofore associated with the same. In particular, the high-k material is annealed in an ambient having a single chemistry of nitrogen and hydrogen, such as ammonia (NH3), to nitride and react unwanted impurities, and an oxidizer to oxidize and densify the high-k material, while mitigating growth of a lower-k material at an interface of the high-k material and an underlying substrate. Additionally, particular temperatures and pressures are utilized within the process so that the risk of an undesired exothermic reaction is mitigated. Annealing the high-k material in accordance with manners disclosed herein has application to semiconductor fabrication processes and, as such, is discussed herein within the context of the same.

Abstract translation: 本发明涉及以大大减少或消除与之相关的缺点和问题的方式退火高介电常数（高k）材料。 特别地，高k材料在具有氮和氢的单一化学性质（例如氨（NH 3））的环境中退火至氮化物并反应不需要的杂质，以及氧化剂氧化和 致密化高k材料，同时减轻在高k材料和下层衬底的界面处的较低k材料的生长。 此外，在该方法中利用特定的温度和压力，以便减轻不期望的放热反应的风险。 根据本文公开的方式对高k材料进行退火，已经应用于半导体制造工艺，并且因此本文在其上下文中讨论。

公开(公告)号：US20050045923A1

公开(公告)日：2005-03-03

申请号：US10649425

申请日：2003-08-27

Applicant: James Chambers

Inventor： James Chambers

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66583 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides, in one embodiment, a method (100) of forming dual work function metal gate electrodes in a semiconductor device. The method includes forming a gate dielectric (105) over a substrate (110) and depositing a mold layer (115) having a first opening (120) therein over the gate dielectric (105). The method further includes creating a first metal gate electrode (125) by depositing a first metal in the first opening (120). Other embodiments include an active device (200) produced by the above-described method and method of manufacturing an integrated circuit (300) using the above-described method.

Abstract translation: 本发明在一个实施例中提供了在半导体器件中形成双功函数金属栅电极的方法（100）。 该方法包括在衬底（110）上形成栅极电介质（105），并且在栅极电介质（105）上沉积其中具有第一开口（120）的模具层（115）。 该方法还包括通过在第一开口（120）中沉积第一金属来产生第一金属栅电极（125）。 其他实施例包括通过上述使用上述方法制造集成电路（300）的方法和方法产生的有源器件（200）。

公开(公告)号：US08076099B2

公开(公告)日：2011-12-13

申请号：US12133963

申请日：2008-06-05

Applicant: James Chambers ,  Jieh-Juen Yu ,  Karl E. Klose ,  M. Neal Guentzel ,  Bernard P. Arulanandam

Inventor： James Chambers ,  Jieh-Juen Yu ,  Karl E. Klose ,  M. Neal Guentzel ,  Bernard P. Arulanandam

IPC: C12Q1/02 ,  C12Q1/37

CPC classification number: G01N33/56911 ,  A61K2039/543 ,  C12Q1/42

Abstract: The instant invention concerns Francisella bacteria mediated degradation of alkaline phosphatase (AP). Detection of AP degradation may be used to determine the presence of Francisella bacteria in a sample. Furthermore, methods for identifying and treating Francisella infections by detecting AP degradation are described. Methods of the invention also concerns methods for treating Francisella infection by inhibiting AP degradation.

Abstract translation: 本发明涉及弗朗西斯细菌介导的碱性磷酸酶（AP）的降解。 AP降解的检测可用于确定样品中弗朗西斯氏菌属细菌的存在。 此外，描述了通过检测AP降解来鉴定和治疗弗朗西斯病菌感染的方法。 本发明的方法还涉及通过抑制AP降解来治疗弗朗西斯氏菌感染的方法。

公开(公告)号：US20070042555A1

公开(公告)日：2007-02-22

申请号：US11205477

申请日：2005-08-17

Applicant: Hiroaki Niimi ,  Luigi Colombo ,  James Chambers

Inventor： Hiroaki Niimi ,  Luigi Colombo ,  James Chambers

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/8234

CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L21/28229 ,  H01L21/31645 ,  H01L21/823857 ,  H01L21/8249 ,  H01L29/517

Abstract: The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).

Abstract translation: 本发明提供了形成栅极电介质的方法，其包括在衬底（110）上形成包括金属和至少一种非金属元素的金属源层（210）。 金属源层（210）形成为具有富含金属的组成。 在金属源层（210）之上形成包括金属的电介质层（310）。

公开(公告)号：US20070037335A1

公开(公告)日：2007-02-15

申请号：US11204235

申请日：2005-08-15

Applicant: James Chambers ,  Luigi Colombo ,  Mark Visokay

Inventor： James Chambers ,  Luigi Colombo ,  Mark Visokay

IPC: H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L29/4966

Abstract: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.

Abstract translation: 同时形成具有各自功函数的不同金属栅极晶体管。 在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。 然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。 然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。

公开(公告)号：US20060267119A1

公开(公告)日：2006-11-30

申请号：US11462573

申请日：2006-08-04

Applicant: Luigi Colombo ,  James Chambers ,  Mark Visokay

Inventor： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC: H01L29/94

CPC classification number: H01L21/823842 ,  H01L29/4958

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract translation: 本发明在一个实施例中提供一种栅极结构（100）。 栅极结构包括栅极电介质（105）和栅极（110）。 栅极电介质包括难熔金属并且位于半导体衬底（115）之上。 半导体衬底具有导带和价带。 栅极位于栅极电介质上方并且包括难熔金属。 栅极具有与导带或价带对准的功函数。 其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。