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    Resistive Memory Devices with Improved Resistive Changing Elements
    21.
    发明申请
    Resistive Memory Devices with Improved Resistive Changing Elements 有权
    具有改进的电阻变化元件的电阻式存储器件

    公开(公告)号：US20090321706A1

    公开(公告)日：2009-12-31

    申请号：US12145608

    申请日：2008-06-25

    申请人： Thomas Happ ,  Franz Kreupl ,  Jan Boris Philipp ,  Petra Majewski

    发明人： Thomas Happ ,  Franz Kreupl ,  Jan Boris Philipp ,  Petra Majewski

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1253 ,  G11C13/0004 ,  G11C2213/79 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/141 ,  H01L45/146

    摘要： An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.

    摘要翻译： 集成电路包括具有电阻变化存储元件的存储单元。 电阻变化存储元件包括第一电极，第二电极和设置在第一和第二电极之间的电阻率变化材料，其中电阻率变化材料被配置为响应于施加电压或电流而改变电阻状态 和第二电极。 此外，第一电极和第二电极中的至少一个包括绝缘体材料，其包括形成在绝缘体材料内的自组装导电元件。 形成在绝缘体材料内的自组装导电元件在将电阻率变化材料切换到不同电阻状态的整个操作期间保持稳定。

    INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE
    24.
    发明申请
    INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE 有权
    集成电路，包括U形形式的访问设备

    公开(公告)号：US20090206315A1

    公开(公告)日：2009-08-20

    申请号：US12033519

    申请日：2008-02-19

    申请人： Rolf Weis ,  Thomas Happ

    发明人： Rolf Weis ,  Thomas Happ

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

    摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.

    摘要翻译： 集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。 集成电路包括将第一接触与第二接触隔离的自对准电介质材料。

    Mushroom phase change memory having a multilayer electrode
    25.
    发明授权
    Mushroom phase change memory having a multilayer electrode 失效
    具有多层电极的蘑菇相变存储器

    公开(公告)号：US07545668B2

    公开(公告)日：2009-06-09

    申请号：US11766831

    申请日：2007-06-22

    申请人： Jan Boris Philipp ,  Thomas Happ

    发明人： Jan Boris Philipp ,  Thomas Happ

    IPC分类号： G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/148 ,  H01L45/1666

    摘要： An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material.

    摘要翻译： 集成电路包括包括至少两个电极材料层的第一电极和包括第一部分和第二部分的电阻率变化材料。 第一部分接触第一电极并具有与第一电极相同的横截面宽度。 第二部分具有比第一部分更大的截面宽度。 集成电路包括耦合到电阻率变化材料的第二电极。

    High density memory array for low power application
    26.
    发明授权
    High density memory array for low power application 有权
    高密度存储阵列，用于低功耗应用

    公开(公告)号：US07515455B2

    公开(公告)日：2009-04-07

    申请号：US11650244

    申请日：2007-01-05

    申请人： Thomas Nirshl ,  Thomas Happ

    发明人： Thomas Nirshl ,  Thomas Happ

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3431

    摘要： A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate of the MOS select transistor. The word line is at an angle with respect to the first bit line and the second bit line. The memory device includes a first resistive memory element coupled between a source of the MOS select transistor and the first bit line. The memory device includes a second resistive memory element coupled between a drain of the MOS select transistor and the second bit line.

    摘要翻译： 存储器件包括第一导电层中的第一位线和与第一位线平行的第二位线。 第二位线在第二导电层中。 存储器件包括MOS选择晶体管和耦合到MOS选择晶体管的栅极的字线。 字线相对于第一位线和第二位线成一定角度。 存储器件包括耦合在MOS选择晶体管的源极与第一位线之间的第一电阻性存储器元件。 存储器件包括耦合在MOS选择晶体管的漏极和第二位线之间的第二电阻存储器元件。

    INTEGRATED CIRCUIT INCLUDING MEMORY HAVING REDUCED CROSS TALK
    28.
    发明申请
    INTEGRATED CIRCUIT INCLUDING MEMORY HAVING REDUCED CROSS TALK 失效
    集成电路，包括具有减少交叉口的存储器

    公开(公告)号：US20090046498A1

    公开(公告)日：2009-02-19

    申请号：US11948204

    申请日：2007-11-30

    申请人： Jan Boris Philipp ,  Thomas Happ

    发明人： Jan Boris Philipp ,  Thomas Happ

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： H01L27/2472 ,  Y10S438/90

    摘要： An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.

    摘要翻译： 集成电路包括第一电极，第二电极，第一电阻率变化材料，在第一界面处接触第一电极，第二电阻率变化材料在第二界面处与第二电极接触。 第一接口和第二接口之间的直接通信路径大于横向距离。

    CONDITIONING OPERATIONS FOR MEMORY CELLS
    29.
    发明申请
    CONDITIONING OPERATIONS FOR MEMORY CELLS 失效
    记忆细胞的调节操作

    公开(公告)号：US20090003035A1

    公开(公告)日：2009-01-01

    申请号：US11778786

    申请日：2007-07-17

    申请人： Jan Boris Philipp ,  Thomas Happ ,  Thomas Nirschl

    发明人： Jan Boris Philipp ,  Thomas Happ ,  Thomas Nirschl

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2213/31 ,  G11C2213/32

    摘要： One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.

    摘要翻译： 本发明的一个实施例涉及一种用于调节具有多个可靠电阻范围的存储器阵列的电阻性存储单元的方法，其中每个可靠的电阻范围对应于不同的数据状态。 在该方法中，访问至少一个电阻性存储器单元的组，该组包括至少一个不可靠单元。 至少一个脉冲被施加到至少一个不可靠的单元，以将至少一个不可靠单元相关联的至少一个电阻移动到可靠电阻范围的最高位置。 还公开了其它方法和系统。

    INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
    30.
    发明申请
    INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE 有权
    集成电路，包括垂直二极管

    公开(公告)号：US20080315359A1

    公开(公告)日：2008-12-25

    申请号：US11766290

    申请日：2007-06-21

    申请人： Thomas Happ ,  Jan Boris Philipp

    发明人： Thomas Happ ,  Jan Boris Philipp

    IPC分类号： H01L29/08 ,  H01L21/336 ,  H01L29/00

    CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/24

    摘要： An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material.

    摘要翻译： 集成电路包括垂直二极管，耦合到垂直二极管的第一电极和耦合到第一电极的电阻率变化材料。 集成电路包括耦合到电阻率变化材料的第二电极和具有接触第一电极的第一侧壁和电阻率变化材料的侧壁的第一侧壁的间隔件。