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    PLURALITY OF 3D VERTICAL CMOS DEVICES FOR HIGH PERFORMANCE LOGIC
    22.
    发明申请
    PLURALITY OF 3D VERTICAL CMOS DEVICES FOR HIGH PERFORMANCE LOGIC 有权

    公开(公告)号：US20220102345A1

    公开(公告)日：2022-03-31

    申请号：US17335563

    申请日：2021-06-01

    Applicant: Tokyo Electron Limited

    Inventor： Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/822

    Abstract: Techniques herein include methods for fabricating vertical stacks of vertical-channel transistors. Vertical channels can be made from an initial epitaxial structure, and electrically isolated at locations to divide the structure into multiple, independent vertical channels. Techniques enable modulating PMOS and NMOS channel composition and channel geometry to match drive currents thereby providing advanced circuit tuning. Advantageously, one process step can be performed per type of epitaxial material to dope epitaxial materials in respective source/drain regions.

    3D SEMICONDUCTOR APPARATUS MANUFACTURED WITH A CANTILEVER STRUCTURE AND METHOD OF MANUFACTURE THEREOF
    23.
    发明申请
    3D SEMICONDUCTOR APPARATUS MANUFACTURED WITH A CANTILEVER STRUCTURE AND METHOD OF MANUFACTURE THEREOF 有权

    公开(公告)号：US20220005805A1

    公开(公告)日：2022-01-06

    申请号：US17124053

    申请日：2020-12-16

    Applicant: TOKYO ELECTRON LIMITED

    Inventor： H. Jim FULFORD ,  Mark I. GARDNER

    IPC: H01L27/06 ,  H01L27/092 ,  H01L21/8238

    Abstract: Aspects of the disclosure provide a method of forming a semiconductor apparatus. A stack of dielectric layers is formed over a semiconductor layer on a substrate of the semiconductor apparatus. Multiple openings are formed in the stack of dielectric layers. Multiple pillars including first sub-pillars and second sub-pillars are formed in the multiple openings. A cantilever structure that includes a first cantilever beam and a second cantilever beam is formed. A cantilever supporting structure that includes a portion of a first subset of the multiple pillars is formed. The first cantilever beam connects the second cantilever beam and the cantilever supporting structure. One of the stack of dielectric layers is removed to expose first portions of the first sub-pillars and second portions of the second sub-pillars. Isolation structures are formed between the first sub-pillars and the respective second sub-pillars.

    SPLIT SUBSTRATE INTERPOSER
    24.
    发明申请
    SPLIT SUBSTRATE INTERPOSER 有权

    公开(公告)号：US20210265254A1

    公开(公告)日：2021-08-26

    申请号：US17097116

    申请日：2020-11-13

    Applicant: Tokyo Electron Limited

    Inventor： Arya BHATTACHERJEE ,  H. Jim FULFORD

    IPC: H01L23/498 ,  H01L21/48

    Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.

    HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING
    25.
    发明申请
    HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING 有权

    公开(公告)号：US20210043519A1

    公开(公告)日：2021-02-11

    申请号：US16705485

    申请日：2019-12-06

    Applicant: Tokyo Electron Limited

    Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME

    IPC: H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786

    Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

    DEVICE AND METHOD FOR DETERMINING WAFER BOW
    28.
    发明申请
    DEVICE AND METHOD FOR DETERMINING WAFER BOW 有权

    公开(公告)号：US20250167023A1

    公开(公告)日：2025-05-22

    申请号：US18511448

    申请日：2023-11-16

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L21/67 ,  G01B7/14 ,  H01L21/66 ,  H01L21/687

    Abstract: An apparatus for measuring bow of a wafer includes a substrate holder including a support surface configured to support a wafer, and an air flow system including a plurality of air outlets in the support surface which are configured to output air for elevating the wafer above the substrate holder. A capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit, each electrode facing the support surface and being spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a wafer elevated by the substrate holder.

    THREE-DIMENSIONAL SILICON NANOSHEET MEMORY WITH METAL CAPACITOR
    30.
    发明公开
    THREE-DIMENSIONAL SILICON NANOSHEET MEMORY WITH METAL CAPACITOR 审中-公开

    公开(公告)号：US20230301060A1

    公开(公告)日：2023-09-21

    申请号：US17971219

    申请日：2022-10-21

    Applicant: Tokyo Electron Limited

    Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

    Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally, and an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally. The semiconductor structure can also include a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor. The lower metal capacitor can include a first lower metal plate that is in-plane with the lower channel of the lower transistor. The semiconductor structure can also include an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor. The upper metal capacitor can include a first upper metal plate that is in-plane with the upper channel of the upper transistor.
    method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having

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